Katmai out of the bag

Intel's Yu gets roadmap frenzy

Intel has provided sneak details of its processor roadmap up until the year 2001 and has also given additional details of the Katmai instruction set it will introduce early next year. Albert Yu, senior vice president in charge of the microprocessor unit, said that the development of additional instructions in Katmai was driven by the need for rich data applications, including MPEG and voice recognition. The Katmai instructions will offer better performance than existing IA32 chips, said Yu. “In the P6 architecture there are key elements including dynamic execution and multitransaction P6 bus. With Katmai we’ve included instructions which offer streaming, additional media instructions and concurrent SIM-D architecture.” He said: “Typically, you fetch, execute and store but with this new capability (streaming), you can fetch, fetch immediately and you don’t have to wait.” That gives up to 10 per cent better performance, Yu claimed. Intel, he said, will introduce its Tanner technology in the first half of next year, aimed at the workstation and server market. That processor will start at speeds of 500MHz and come with various cache sizes and different chipsets. In the second half of next year, its Cascade .18 micron technology will be arrive. It will offer “much higher” speeds than 500MHz and have integrated cache to give better price performance, Yu said. Soon after Intel introduces the Katmai chip, it will introduce its Coppermine technology, said Yu. That will be Katmai based but come on .18 micron process technology, arrive at speeds of greater than 500MHz and come with integrated second level cache. Intel will introduce another Celeron running at 366MHz early next year in different packaging. Yesterday, Yu said it would introduce a 370-pin package towards the end of the year. All Slot One based Celerons will eventually migrate to this packaging, he said. In the mobile sphere, Yu said that it will introduce higher speeds than 333MHz. Yu claimed that Intel was still on track for its Merced and its McKinley microprocessors. “We aim to get production in the middle of 2000 and at the moment we’re doing exhaustive testing,” he said. “We have just about every OS working in simulation and we’re moving on track.” He said Intel had more than one Merced slated. Its McKinley chipset, he said will arrive in the second half of 2001 and use the same instruction set as the Merced. “We have another one beyond that [McKinley] and the work has already begun,” he said. ®