Hot Chips The systems business is largely dominated by x86-based machinery these days, but Big Blue's mainframe unit is hanging in there after five decades and is still a bit of a mint.
You put in $1bn every two years for hardware development, as IBM has done with the new System zEnterprise EC12, and you take out $7bn in ridiculously profitable hardware sales over the next two years, and probably as much revenue from monthly systems software at even higher profit margins over those same two years.
You can laugh all you want about how stodgy mainframes are, but IBM CEO Ginni Rometty is laughing all the way to the bank, as are IBM's shareholders, who benefit from billions of dollars in dividends and share buybacks that are paid in part by the mainframe biz.
Rometty is probably breathing a sigh of relief as well, with the prior z11 mainframe cycle running out of gas as she took the helm in January. She will get to close out her first year running IBM with what will presumably be a big bump in revenues now that the "zNext" or z12 machines (depending on what code-name you want to use) are coming to market earlier than expected.
The word on the street was that IBM would announce the zEnterprise EC12, the high end of the z12 product line, sometime in late September or early October with shipments ramping through the fourth quarter. But, according to sources inside IBM, the chips and systems were ready early and so Big Blue decided to get the machines out the door on the same day that the company is talking up the feeds and speeds of the z12 processor at the Hot Chips conference in Silicon Valley.
IBM told El Reg about the zEnterprise EC12 mainframe ahead of the Hot Chips presentation and did not want to spoil the show by giving out all the gory details of the z12 chip. But Jeff Frey, an IBM Fellow and and the CTO for the System z division who designed the z11 and z12 systems, gave El Reg some of the basic stats of the chip and talked about the new system that is built around it.
The z12 chip is implemented in a 32 nanometer high-K metal gate process and fabbed by IBM itself at its East Fishkill, New York foundry. The z11 chips used a 45 nanometer process, and the shift to 32 nanometers has allowed IBM to get twice the transistor density for logic and on-chip cache memory.
The z12 chip was designed to scale up to 6GHz, which is roughly twice as fast as the clock speed on your average Xeon or Opteron processor, but is coming out at 5.5GHz initially. The z11 had four cores on a single die running at a top speed of 5.2GHz, but the process shrink is allowing IBM to boost the core count by 50 percent to six cores while also cranking up the clocks a bit.
IBM is doing other things in the z12 chip to boost single-threaded application performance as a batch engine, which is critical for customers. This includes boosting the sizes of on-chip caches and putting together a second generation out-of-order execution pipeline, which debuted with the z11 chips.
The L2 instruction and data caches have been boosted to 2MB, up from 1.5MB with the z11 chips, and L3 embedded DRAM cache is now 48MB, double that of the z11. On the outboard L4 cache controller and SMP hub that glues processors on a system board together (IBM calls them books) and multiple books to each other, the L4 cache has also been boosted 384MB, double that of the zEnterprise 196 machine announced two years ago.
The z12 chips also have more relative branch execution units to help speed up the threads, and mainframe compilers can now issue prefetch directives to the engines to help applications do a better job of getting instructions and data lined up to push more work through the z12 chip.
When you add it all up, the single-engine performance of a z12 chip is about 25 per cent higher than on the z11 that preceded it. IBM has not released official MIPS ratings (a throwback to the days when IBM actually counted the millions of instructions per second that a machine could process) for the z12 engines, but given that the top-end core in a z11 processor delivered 1,200 MIPS, that puts the z12 core at around 1,600 MIPS.
IBM's System zEC12 mainframe
"We are hitting the limits of physics in many cases," says Frey, "but what you see here with the zEnterprise EC12 is IBM not giving up on single-thread performance."
IBM has also added more processors to the System z complex and done other tricks to boost the SMP scalability with the zEnterprise EC12 behemoth.
Interestingly, the zEnterprise EC12 is the first IBM system to support transactional memory, which is an overlay atop standard DDR3 main memory that can reduce software locking across multiple execution units.
IBM calls it Transaction Execution Facility, and the idea is to have the processors and the SMP hub controller do "opportunistic locking" of main memory blocks instead of software locking as applications run. You do the transactions fast and then see if you needed to lock after the fact, and most of the time you don't.
If you did hit a locking condition, you go back and redo the work. The upshot is that the overall throughput of the machine can increase even if there is a huge stall every once in a while. We'll try to get more information on this at Hot Chips.
This transactional memory will help boost the performance on multithreaded applications where there can be contention, such as with DB2 databases and Java Virtual machines. Frey says that the combination of higher clocks, bigger caches, and transactional memory can boost multithreaded performance on an zEC12 box by as much as 45 per cent compared to a z196 machine.
Also helping DB2 and Java performance in the zEnterprise EC12 is support for 2GB page frames, which helps DB2 buffer pools and Java heaps take bigger bites of memory and do less swapping. Page frames topped out at 1MB with the prior zEnterprise 196 box.