After skipping a generation of upgrades, Motorola outlined its plan to steer the G4 chip back on course at Microprocessor Forum in San Jose yesterday.
David Bearden of Motorola's Somerset lab outlined a new G4 design which makes much use of cache and process technology improvements to take the chip beyond the 1GHz frequencies of its x86 rivals. But there's no news of when these new chips, which use the umbrella name Apollo, will appear.
But Bearden was vague on speeds, and Apple watchers hoping for firmer timescales, and specific details of speeds and feeds for the much anticipated G4 Plus were disappointed, and might remain so for some time. The next speed bump is Voyager - the G4 Plus - outlined at last year's Microprocessor Forum: Apollo is the successor to Voyager.
The Apollo G4 will use IBM's SOI (Silicon-on-Insulator) technology and be based on 0.18 micron process, Bearden said, this and a deeper pipeline will permit the higher clock speeds. He said that the SOI method added 22 per cent performance improvement over bulk CMOS alone. Apollo will feature a wider, 256-bit path between on-chip caches, on-die L2 cache of 256KB and up to 2MB of external L3 cache. Bearden cited power consumption of under 10W at 666MHz and under 23W at super-1GHz frequencies.
At least Apple, the largest volume customer of G4s, will take a crumb of comfort here, as the low power consumption and the accompanying lower heat dissipation will ensure future versions of its fanless desktops remain silent.
And that's yer lot. Bearden didn't hang around to take questions, and perhaps wary of an ambush hatched from nearby Cupertino, took off as soon as he'd spoken. ®