The fur should be flying at this year's International Electron Device conference in San Francisco on 12 December as rivals AMD/Motorola and Intel climb atop the soapbox to present details of their rival 130nm processes in back to back presentations.
Chipzilla's batting first at 1510 on the 12th, with AMD/Motorola following directly on at 1535.
Intel's P860 process has six layers of copper interconnects. Effective gate length is a tiny 70nm, SRAM cell size is just 2.09 square microns - almost three times smaller than the current SRAM cells used in the PIII and P4. Chipzilla reckons the 130nm process will be 65 per cent faster then that its current 180nm process
AMD and Motorola say their HiP7 process is aimed at everything from GHz processors to low power mobiles. Dual and single inlaid copper metallisation allows more levels of interconnect than the Intel process (nine) although gate length is a tad bigger than the P860 process at 80nm.
More detailed specs of the rival processes are available at Chip Architect.
Back in 1989, the world gaped in wonder at Intel's one micron P648 process. With a gate length of one whole micron, an SRAM cell was a stonking 220 microns square. It needed 5V to drive it (compared with 1.3V for the P860) and only offered two levels of interconnect. ®