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IBM extends PowerPC roadmap to 2GHz+

Swallows pride, signs up for Motolora's AltiVec

IBM has updated its PowerPC roadmap with plans to take its G3-class processors to 2GHz and beyond - a move that will see the company finally re-seal the breach with PowerPC partner Motorola and incorporate AltiVec technology into its microprocessors.

Alas, Big Blue's timeframe for all this is decidedly vague - the company appears to have taken another leaf out of Motorola's book here - but the basic plan calls for a shift up from the current 700MHz peak speed of the PowerPC 750CXe to 1GHz and up, followed by a later shift up to 2GHz and beyond.

The initial move centres on the incorporation of some key processor technologies, most of which stem from IBM and Motorola's attempt to re-align their embedded processor development efforts a couple of years back, the 'Book E' initiative.

So, the next generation of PowerPCs from IBM will be based on a multi-core architecture designed for symmetrical multiprocessing (SMP). IBM's 32- to 256-bit Crossbar CoreConnect bus will be used to tie these multiple processor cores - all on a single CPU die - together.

In addition, these 1GHz+ chips will support the RapidIO bus, which brings to chip-to-chip communication a data throughput of 10Gbps, and, as IBM's roadmap puts it, an "integrated SIMD engine". That has to be a reference to Motorola's AltiVec vector processing system, called Velocity Engine by Apple.

Long-time PowerPC watchers will appreciate the irony. AltiVec was the cause of IBM and Motorola's first spat over the direction of PowerPC development. Motorola wanted it, IBM didn't, which is why Big Blue has never developed a version of the PowerPC 74xx family - aka the G4 - of its own.

We suspect its attitude changed when it won the contract to develop a PowerPC chip for Nintendo's next-generation Gamecube 3D games console - a perfect application for AltiVec if there ever was one. We speculated at the time that IBM might come nosing around AltiVec, and it looks like we were right.

Whatever, IBM's next-generation architecture sounds suspiciously like Motorola's own evolution of the technology, codenamed Apollo and G5. IBM's version is planned to be produced at 0.13-0.10 micron, using low-k dielectric and silicon-on-insulator technology. IBM already uses SOI, and while Motorola doesn't, it is expected to with Apollo.

RapidIO, meanwhile, appears to be a replacement for Motorola's 128-bit MaxBus, originally designed for the G4 but never implemented to its fullest degree. MaxBus may simply be Motorola's name for RapidIO, or it may be the basis for the standard, we're not sure - perhaps someone from the chip company would care to put us in the picture. For its part, IBM seems a recent convert - it only joined the RapidIO Trade Association at the end of April.

Looking beyond this generation, to the 2GHz+ parts, IBM talks about an "ultrascalar... Enhanced PowerPC Architecture", which extends the multi-core approach to a complex system in which cores operate in parallel on a switched version of CoreConnect and talk to the outside world via a "new high-speed interface".

It's a tad pie-in-the-sky, but it doesn't sound all that far off IBM's Cell project, announced recently with Sony and Toshiba. Whether Motorola's own roadmap will move this way isn't known, but given both companies will be starting again from the same base - call it Apollo - they may not diverge too far this time.

Some of the blurb associated with the roadmap claims this "Enhanced PowerPC Architecture" is Book E, but the roadmap itself notes that IBM's sub-500MHz PowerPCs were based on Book E architecture, so clearly Book E is something of a moving target. We suspect that Book E is simply a baseline description of a PowerPC processor that, like the chip itself, has evolved as new technologies have emerged. Early Book E parts were 32-bit, for example, but next-generation ones will be 64-bit. Despite that difference, they'll still both be Book E processors - provided they retain backward compatibility.

IBM's roadmap covers parts for networking, storage, consumer and server applications. The latter suggests some alignment with Big Blue's server-oriented POWER family of processors, the main stem from which PowerPC originally branched off. ®

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