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Project Jackson breaks cover – Xeon in 2002, Itanic later


Intel Developer Forum Intel took the wraps off Project Jackson today, the multi-threaded chip technology we told you about back in February. It's the art of making one processor behave like two or more logical processors, which adds a little extra hardware overhead to the chip but offers the possibility of much better parallelism. And it's probably Chipzilla's biggest design innovation since it put the x86 charabanc on Risc internals with the Pentium.

In preference to the standard academic term for this architecture, SMT (simultaneous multi-threading), Intel calls it Hyperthreading. The first implementations will appear in Xeons, or 'Xeon MP' next year, which will have two logical processors. Intel also says that SMT will find its way into the Itanic family eventually.

Intel claims that the SMT Xeon offers a 30 per cent improvement over the same processor with the threading turned off. That's running MS IIS. Figures of 23 per cent for Exchange and 22 per cent for SQL Server were also offered. Intel couldn't or wouldn't give figures for a two-logical-processor, but single-chip Xeon MP against a two-processor Xeon SMP. Which is fair enough at this stage, as the two will be priced differently.

When we ran over the history of SMT earlier this year, Dean Tullsen - who co-authored the landmark academic paper that put SMT at the top of the academic design agenda - told us he'd been advising Intel on various techniques (he couldn't say which, being in purdah).

Tullsen it was who worked with DEC on making Alpha multi-threaded in 1995. With Compaq sending the Alpha EV8 to sleep with the fishes (see Alphacide articles passim) Xeon MP will become the first processor to be generally available in volume systems.

The first Jackson will incorporate an 8KB L1 data cache, a 256KB unified L2 cache and 1MB of L3 cache on the chip. The Xeon MP will alternate between the two logical processors so if one processor misses a fetch cache request it goes to the other. If they both miss it will alternate between the two. There's an eight-way associative cache line for resolving conflicts on a LRU basis. Of course Jackson-ized Xeons will share data in their caches. When conventional SMPs encounted a cache miss, they have to hop across the bus to sniff (we believe the technical term is 'snoop') the instructions out the cache of another processor. That's one of the reasons why SMT is a big performance win.

The other is the parallelism: the processor makes more efficient use of deep pipelines. There slides from today's SMT sessions are online here.

OS vendors - who've been briefed about Jackson for almost a full year now - will need to make few tweaks, but those tweaks help. There will be some scope for processor affinity, it emerged.

Engineers in the packed introduction had plenty of questions. If Xeon MP was so dandy, wouldn't this affect low-end Itanic?

Gosh, no, came the predictable reply. But Jackson chips will run hot - very hot. Although peak power consumption is only slightly increased, the average power consumption is "greatly increased", because the processor is being run much closer to its theoretical maximum throughput. Of course that's better than having it draining the grid while simply throwing instructions away. ®

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