Analysis The findings of the 2001 International Technology Roadmap for Semiconductors (ITRS) may explain why the world's largest chip foundry, TSMC, is causing some of its key customers, including Nvidia and Transmeta, to complain about its ability to punch out sufficient volumes of 0.15 micron and 0.13 micron chips.
The ITRS is the Semiconductor Industry Association's attempt to chart the future evolution of the microchip from the progress that its members are actually making. The SIA polled 800 industry specialists from the US, Europe, Japan, Korea and Taiwan to produce a consensus view of where the chip business is heading.
For example, the ITRS reckons we'll hit 0.022 micron technology in 2016, having been through 0.09 micron in 2004 and 0.065 micron on 2007.
Low k, high efficiency
The ITRS forecast combines some optimistic and other, more conservate predictions regarding the implementation of new process technologies. One of the latter is the use of low-k dielectric materials, a key part of the application of copper interconnects, at sub-0.18 micron chip fabrication processes.
Low-k dielectric films are used to insulate copper interconnects from their surroundings, ensuring that less signal bleeds out of each connection and into others. Such insulators are key to maximising the efficiency of ever more compact micro-circuitry and are widely seen as an essential successor to silicon dioxide insulators.
According to ITRS officials, speaking at the publication of the latest ITRS on Wednesday, the development of low-k dielectrics hasn't happened as quickly as the body originally forecast.
"Unlike practically anything else that we have ever been looking at, the low-k area is one where there are many viable candidates on the table - all at one time," said Robert Doering, a senior fellow at Texas Instruments and a member of the ITRS Committee.
The upshot: progress on implementing and refining low-k dielectric materials has slowed as chip makers struggle to work out which of the "viable candidates" to back. The longer the industry takes to define the key methods of implementing low-k dielectrics, the longer it will be before they are refined and the more time it will take to increase chip yields.
The implementation of low-k dielectrics is a complex mix of process and materials, but two methods appear to be leading: applying the insulator films using traditional chemical vapour deposition (CVD) tools or using a newer 'spin-on' process, which applies the material by dropping it onto a rapidly-rotating wafer.
Lost and foundry
TSMC uses the former process. Now, Nvidia and Transmeta - and, we hear, VIA and Broadcom - have complained about the yields TSMC is getting.
Transmeta, for instance, blames the problems TSMC is having implementing its CVD-based system for the late arrival of its 0.13 micron Crusoe processors, the TM5500 and TM5800. Both were announced last July, but will only begin to ship by the end of the current quarter - ie. by the end of December - Transmeta has admitted. The 0.13 micron process is central to Transmeta's plan to clock its chips up to 1GHz and beyond.
Nvidia, meanwhile, is believed to have gone so far as to sign up UMC as an alternative supplier. Given Nvidia's long relationship with TSMC and the cost and time required to bring another company's fabs on stream, a process requiring much preparation and quality assurance, that's not a move you would expect the company to make, and it suggests that it is very unhappy with TSMC's ability to deliver sufficient volumes of 0.15 and 0.13 micron chips.
The choice of UMC is interesting because - as it announced earlier this year - it is using the spin-on method rather than CVD. It reckons spin-on will allow it to produce finer yet more efficient low-k dielectric films and thus enable more compact chip circuitry. The downside: the spin-on process is more costly to implement than CVD, which is essentially an extension of existing technology.
That there are broad issues with low-k dielectric yields is the ITRS committee's decision to "decelerate" the technology's arrival in the mainstream.
Some industry watchers have taken Nvidia's move as a sign that the chip designer may no longer believe CVD to be the best way to achieve high yields and is thus backing the alternative - in other words, that TSMC may not be able to deliver 0.15 and 0.13 micron copper chips with low-k dielectrics commercially, for the moment at least.
Nvidia may be a long-term TSMC partner, but if UMC can produce more 0.15 and 0.13 micron chips, more cheaply, Nvidia will have little choice but to pursue the more economic choice. Quite apart from its own-brand graphics and chipset products, it has been contracted to supply parts for Microsoft's Xbox console. The ongoing revenue and profit grow it hopes to achieve are predicated on its ability to supply sufficient chips to Microsoft and its other partners. And to maintain its consistently high share-price.
The last thing Nvidia wants is for Microsoft to admit publicly that it can't make enough Xboxes and to be blamed for it. Look at the embarrassment caused to Transmeta when Fujitsu and Sony both laid at its door the delays they'd been forced to make to their notebook roll-out plans.
TSMC vs UMC
Of course, Nvidia's move to UMC shouldn't be taken as ringing endorsement of the foundry's approach to low-k dielectrics, but it suggests that Nvidia feels it has to back more than one horse in the race.
It's also a very loud message to TSMC to work harder to solve its yield problems. The company can, of course, install extra equipment, but with yields as low as they appear to be, that's not going to do anything positive for its bottom line. TSMC has to get yields right up to 95 per cent or more to make the kind of profit it has achieved in the past - which is particularly important when it's climbing out of the biggest downturn in the industry's history.
Unlike Intel and, to an extent, AMD, both of whom are said to be having some difficulty with their own 0.13 micron processes, TSMC can't afford to bank-roll low yields just to show that it's at the cutting edge of chip fabrication technology.
It's won't be plain sailing for UMC either, but increased orders from Nvidia will show that spin-on is proving a better technology than CVD, Mark Osborne, News Editor at Semiconductor Fabtech magazine told us.
And so to 0.10 micron
Getting low-k dielectrics right at 0.13 micron is essential if the industry is to make the next step, to 0.10 micron - which, if anything, will be harder to achieve than 0.13 micron. No wonder then that the ITRS has put back its microprocessor process roll-out forecast back from two years to three. ®