This article is more than 1 year old
IBM boffins boost combo computing, wireless chips
Products will be way faster, using much less power
IBM chip scientists have figured out how to bring the company's high-performance processor construction technology and wireless semiconductor materials together.
The discovery paves the way for better integration between computing and communications chips, the company said. The result: a 300 per cent increase in performance and an 80 per cent reduction in power consumption over thin-silicon bipolar technology.
IBM is a keen proponent of silicon-on-insulator (SOI) technology, which boosts processor performance by improving the electrical characteristics of component transistors. That also reduces the power required to switch each transistor. AMD, incidentally, takes the same view. SOI is used to make its Athlon 64 chips, and IBM's own 64-bit PowerPC 970, dubbed the G5 by Apple.
Unfortunately, while SOI works will with processors, it's less well suited to radio frequency chips of the kind used in wireless networking products, for example. They use bipolar Silicon Germanium (SiGe) as their semiconducting material. SiGe can be used alongside CMOS materials, the basis for processors, and the technique is already being used to build single-chip wireless solutions. However, the processing component can't utilise SOI for improved performance - SiGe bipolar transistors can't be constructed on top of a thin SOI wafer.
Until now, says IBM. The new process lays a thin layer of SiGe on top of the SOI wafer, forming the basis for the bipolar transistor:
Says IBM: "Electrons come down from the poly-silicon emitter, accelerate through the SiGe base, and make a turn in the SOI layer towards the collector contact electrode. With zero or low voltage applied to the SOI wafer, the current path in the SOI is long, which results in low electric field in the SOI and makes the device suitable for high voltage applications (pink arrow); with high positive voltage applied to the SOI wafer, the collector contact is virtually extended all the way to the back of the SOI layer under the emitter. The current path is thus shorter (green arrow), making the device suitable for high speed applications."
IBM now has to perfect the process and start adding CMOS circuitry alongside the SiGe transistors. Then the work toward commercialising the technique can begin. The company reckons we'll see combined computing and communications chips using this technique within the next five years.
The results will be not only cheaper gadgets - thanks to fewer component chips - but more powerful ones that also provide longer battery lifetimes. IBM's work should also make it easier to integrate wireless connectivity into computer chipsets. ®
NEC boffins create 'stable' nanotube fab process
IBM boffins boost chip performance by 65%
'Smart' glues to drive unleaded chips
Micro-engines to power next-gen PDAs, PCs, phones
AMD and Intel scientists outline future chip tech
AMD 'super' SOI to boost chip speeds by 30%