Intel is having a tough time convincing the world that it's 90nm chip manufacturing process hasn't run into difficulties, so it's already starting the public relations offensive intended to push its upcoming 65nm process, due to go live in 2005.
The chip giant today said it had built a working array of memory cells using said process, which incorporates strained silicon, eight layers of copper interconnects and low-k dielectric insulators.
These features will be a key part of the 65nm chips Intel punches out using the new process, and the message it wants us to take away with us is that if it can get a working 4Mb SRAM cell using the technology, it will easily be able to do so with the heirs to 'Prescott', its 90nm Pentium 4.
Indeed, it reckons it will be the first chip maker to "produce 65nm generation products in 2005". Of course, producing chips and producing enough for computer makers to ship kit are two very different things, as the gap between Intel's Prescott 'revenue shipments' and the availability of Prescott-based PCs shows. The first are due by the end of 2003, the second lot aren't expected to appear until February 2004.
Likely processors to be made using the 65nm process include dual-core Pentium, Xeon and Itanium chips roadmapped to appear in the late 2005 timeframe - as indeed will AMD and possibly Sun. Motorola will probably be there already.
Intel has scheduled the next process transition but one, going down to 45nm, for 2007. At that size, it expects to make use of new materials and high-k dielectrics.
Intel also talked up its lithography expertise, explaining how its 193nm tools will be used to create 65nm dies using clever technology to distort the image of the circuitry that's shined upon the wafer in order to compensate for the optical limitations of said tools.
It expects to use other techniques, most notably phase-shift masks to get down to under 40nm using 193nm tools rather than shift down to 157nm technologies. This way is cheaper, it reckons. For 32nm and beyond, Intel may abandon 193nm for Extreme UV lithography. That's one "possible" move Intel Director of Process Architecture and Integration, Mark Bohr, said today. ®