This article is more than 1 year old

AMD dismisses Intel ‘high-k’ transistor tech

But strained silicon and metal gates are OK

AMD this week cocked a snoot at rival Intel's pursuit of high-k dielectric materials as the foundation for future, 45nm process technologies.

The chip maker's own solution is a three-gate transistor design, which it discussed at this year's IEEE International Electron Devices Meeting, held in Washington, DC. AMD also re-iterated its belief that silicon-on-insulator technology remains the best foundation for today's chips - and tomorrow's.

Central to the new design is the use of full-depleted SOI structures, AMD said. It detailed its work on FDSOI back in June, after announcing it was working on the technology earlier this year.

Current SOI implementations use partially depleted silicon films, which are easier to make than fully depleted structures but less efficient. The different physical structures of the silicon and the insulator can lead to electrical imperfections where the two materials meet, slowing the transistor down and allowing current to leak. Essentially, the silicon ceases to have a pure crystalline structure, degrading its performance as a semiconductor. The thinner the SOI layer, the worse the effect. Using FDSOI, however, should allow AMD to produce very thin SOI layers that don't suffer from the performance degradation.

Swiping at its rival, AMD said its new transistor is "not dependent upon the use of so-called 'high-k' gate dielectric materials, which have been shown to have negative effects on some aspects of transistor performance".

Intel recently touted just such a material as the foundation for its 45nm process, internally codenamed P1266.

That said, the two do agree on the use of metal gates at the 45nm node. AMD is committed to using nickel-silicide rather than polysilicon, the material from which both Intel and AMD make today's processors. Intel, which announced its plan to use metal gates last month, will not say what material it plans to use.

Both companies also concur on the need for strained silicon. But while Intel is implementing the technique in its 90nm process, AMD will wait until it gets to 45nm to fill the gap between source and drain with strained silicon to boost electron flow. ®

Related Stories

Intel claims high-k material will slash chip power hunger
AMD and Intel scientists outline future chip tech
AMD 'super' SOI to boost chip speeds by 30%

More about


Send us news

Other stories you might like