Codename cornucopia reveals Intel's 65nm CPU plans

More CPUs, more supported L2 cache sizes


Intel may be preparing to segment its next-generation 65nm desktop and mobile processor lines by taking a leaf out of arch-rival AMD's book and offering chips with a range of different cache sizes.

So we might conclude from the list of upcoming Intel CPUs for 2006 and 2007 published by Tom's Hardware. The list is a veritable dictionary of new codenames, but you can see some patterns begin to emerge.

'Conroe', Intel's already announced next-gen desktop chip, is due in Q3 2006, according to recent roadmap leaks. It will implement two cores on a single die, with 4MB of L2 cache shared between them. Alongside Conroe, Intel will offer 'Allendale', this time with 2MB of shared cache.

Conroe's mobile sibling is 'Merom', again well known to Intel watchers. Like Conroe, it's known to contain 4MB of shared L2. However, it will also be offered with 2MB of L2. Unlike Allendale, its desktop parallel, this second Merom doesn't have its own codename, at least not according to the Tom's Hardware list.

It will be followed in "mid-2007" by 'Stealey', a single-core mobile chip with 512KB of L2. Interestingly, the list has 'Cedar Mill', the single-core desktop part due early next year, down with 512KB, 1MB and 2MB of L2. Intel has already said, Cedar Mill will ship with 2MB of L2, but not the lower cache sizes.

Ahead of Stealey, in early 2007, Intel will allegedly offer 'Millville', a single core part with 1MB of cache. Whether it's aimed at desktops or notebooks isn't clear.

Mid-2007 will see the debut of 'Kentsfield', a dual-core chip created from two single-core dies connected within the same package, much as two Cedar Mills will next quarter be combined to form the dual-core 'Presler'. Kentsfield has 4MB of cache, suggesting its single-core sibling - its equivalent of Cedar Mill - will have 2MB of L2. Whether that single-core chip is Milville isn't clear, but it could be.

What these many chips reveal is a shift toward different incarnations of the same CPU being offered with different L2 cache sizes. It's a logical move, now that Intel is de-emphasising clock speeds. AMD already uses 512KB and 1MB cache sizes to offer chips at the same clock speed but different model numbers, and it looks like Intel will do the same.

In the server space, the Yonah-derived 'Sossaman' is well known, as is the Merom/Conroe-based server chip 'Woodcrest'. Woodcrest has 4MB of shared cache and two dies on a single die. The first quad-core chip is due "mid-2007", implemented using multiple dies, and codenamed 'Clovertown'. It has 4MB of cache, the report claims. ®


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