Nehalem Day Intel's "Nehalem EP" Xeon 5500 series of processors for two-socket servers were announced this afternoon. Finally. Now, the server market can breathe a sigh of relief and set about the difficult task of trying to peddle better boxes in a worsening economy. Which sure beats trying to sell last year's machines this year.
Today, in Santa Clara, California, Intel general manager Pat Gelsinger characterized the launch of the Xeon 5500 chips and their related chipset, the "Tylersburg" 5520, as the most important server chip launch since the Pentium Pro was introduced back in 1995.
Back then, Gelsinger explained, the Pentium Pro was the first x86 chip that had native multiprocessing capability built into it. (Some niche server vendors back then had created their own chipsets to glue multiple Pentium chips together to make SMP servers, of course, but Gelsinger didn't mention that). It was also the first Intel chip to feature out-of-order execution, a nifty technology that had been experimented with on RISC and other processors to boost performance.
The Pentium Pro laid the groundwork for the standard, high-volume server platform, Gelsinger explained, which is absolutely true, and by the time it evolved into the Xeon family, the dot-com boom exploded and x86 rack servers started flying out of the factories of Intel's partners like a hotcakes. This will show you how much things have changed since then.
Back in 1995, when the Pentium Pro was launched, Intel's partners pushed maybe 700,000 servers a year, and those machines represented less than 10 per cent of the global revenue for servers. These days, the vast majority of the 8 million servers shipped per year are x64 machines, and these boxes account for a little more than half of all revenues.
It will take another dozen years before we can declare the Nehalem EP server launch to be as "transformational" as Gelsinger and his peers at Intel want us to believe it is, but the fact is that the Nehalem EP chip is exactly the high-volume, high-performance, energy-efficient chip that should have been launched years ago, not today.
Intel's customers have Advanced Micro Devices to thank for the long road from the appallingly-bad Paxville Xeon DPs back in late 2005 to the Nehalem EPs launched today. Had AMD not been aggressive with the Opteron design - including 64-bit memory extensions, multicore capabilities, point-to-point interconnection between processors, memory, and I/O, integrated memory controllers, and lots of other goodies - Intel would probably still be talking about 32-bit Xeons and the inevitable move to 64-bit Itaniums.
There are seventeen different Nehalem EP chips, including a dozen Xeon 5500 parts for two-socket servers, three Xeon 3500 variants that plug into uniprocessor servers, and two low-voltage parts that are intended to be used in embedded applications. A couple of the chips have only two cores, but most of them have four cores on the die. The chips have either 4 MB or 8 MB of L3 cache and have bandwidth on the QuickPath Interconnect interfaces that ranges from 4.8 GT/sec to 6.4 GT/sec.
The old Xeon architecture had a frontside bus that fed out to elements on the system board, which ran at a certain speed (800 MHz, 1.33 GHz, whatever), but Intel has to measure the billions of transfers per second that QPI can handle because it isn't just pointing in one direction, but in many directions.
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