Intel tunes Nehalem for HPC
Super NEC pact
SC09 Chip maker Intel is tweaking its future eight-core Beckton Nehalem EX processors, making a special version aimed just at HPC customers.
On Monday at the SC09 supercomputing trade show in Portland, Oregon, Intel also announced a partnership with NEC to build Xeon based suppers. NEC already uses Intel's Xeon and Itanium processors for its various Express5800 servers and fault-tolerant machines.
Intel is being a bit coy about the specifics of this HPC variant of the Nehalem EX, which will presumably be called the Xeon 7500 when it comes to market. All that an Intel spokesperson would confirm to El Reg is that the future HPC variant of the chip would come with six cores and would therefore be able to run those cores at a higher clock speed than in the full eight-cored version.
It is reasonable to speculate that Intel may simply sort through the Xeon bins and find Nehalem EX parts that have six out of eight cores working and that can run at a higher clock speed; it would be most unusual for Intel to actually create a six-core layout of the Nehalem EX design. To cut back on power dissipation, it would not be at all surprising to see some of the cache memory on the Nehalem EX disabled to allow further cranking of the clocks on this six-core HPC variant.
As El Reg reported back in May when Intel pushed production and shipment of the Nehalem EX chips to OEM server customers to the end of the year, and therefore server makers were not going to get them out the door until early 2010 at best, Intel has been quiet about exactly at what clock speeds its big bad chips would run. The Nehalem EX chips are implemented in a 45 nanometer high-k metal gate process and cram over 2.3 billion transistors on the chip.
Each of the eight cores has HyperThreading (yielding two virtual threads per core) and can also support TurboBoost (which allows for core clocks to be dynamically increased in speed if a certain number of cores are shut down). The Nehalem EX processors have four QuickPath Interconnect ports per socket, and have a memory-buffering technology called Scalable Memory Interconnect (code-named Millbrook) that acts as a buffer between the processors and their 16 DDR3 memory slots per socket. To conserve heat and allow more clocks on the six-core Nehalem EX variant, Intel might also be tempted to cut out some memory capacity and those buffer chips.
Intel had no comment on any of these possibilities. But the company does have a habit, as it has done with the Nehalem EP Xeon 5500s launched in March, of cutting out features to lower power consumption and heat dissipation.
There is some talk buzzing around SC09 that the shipment date for the Nehalem EX chips has slipped into early next year, but the Intel spokesperson reiterated that Intel planned to ship the chip to server makers by the end of 2009, that the launch date had not changed, and that Intel expected server partners to begin shipping systems based on Nehalem EX starting in the first half of 2010.
Back in June, IBM committed to getting its eight-socket Nehalem EX System x box out the door in May or so, and Silicon Graphics said today at SC09 as it launched its Altix UV UltraViolet shared-memory supers that are based on the Nehalem EX that it planned to start initial shipments in the second quarter with volume shipments in the third quarter.
In a separate announcement, Intel said that it would partner with NEC on designing new supercomputers based on future Xeon products. NEC, of course, makes its own SX vector processors, which were at the heart of the Earth Simulator massively parallel vector machine that ruled the Top 500 ranking of supercomputers for a while in the prior decade.
But NEC has had a tough time making money with the SX line and even pulled out of a massive $1.2bn project called Keisoku that was to see NEC and Hitachi make a new vector engine and Fujitsu add-in Sparc engines to forge a hybrid vector-scalar machine that scales to 10 petaflops.
NEC, it seems, is shopping around for cheaper vector math. Intel and NEC are vague about the partnership and what it may develop, but NEC is apparently interested in the AVX vector math extensions to the Xeon chips that are coming with the Sandy Bridge Xeons in 2010. NEC didn't say it would use Sandy Bridge Xeons or commit to any particular Intel product or HPC roadmap. It did say, however, that it intended to continue to sell and support the SX vector machines.
Finally, Intel said today that it would have a beta program for its Ct programming technology, which helps parallelize C and C++ applications to take advantage of multiple cores and threads, out by the end of 2009. You can find out more about Ct here. ®