At the meeting this week, Patla gave out a little more detail on the "Interlagos" Opteron 6200s, which will be two Opteron 4100s in a single G34 socket, and the Opteron 4200s, which will plug into the C32 socket (a modified version of the Rev F socket). Here's the before and after:
As you can see, the Bulldozers will have double the L2 cache, at 1 MB per core, plus a 33 per cent bump in L3 cache memory, to 8 MB per die. So on Interlagos chips, which put two Valencia's on a package, the total L3 cache per socket will be 16 MB. The future Opterons will also have a Turbo Core mode that allows them to bump up their clock speed as workloads dictate by as much as 500 MHz, even when all of the cores on the chip or in the socket are being used to do work. (To use Turbo Core mode on Intel chips, you have to shut down all the cores but one on the chip, and you only get a nominal increase in clock speed during the time the cores are sleeping).
As AMD said earlier this year, the Bulldozers, socket for socket, are expected to offer about 50 per cent more oomph with a 33 per cent increase in core count over the Opteron 4100s and 6100s - and do so in the same power bands of 65, 80, and 105 watts. Patla held to that performance increase this week at the financial analysts meeting. And he also provided some insight in how this will be accomplished.
First, the memory controller on the Bulldozer Opteron processors will support 1.6 GHz memory, boosting clock speed by 20 per cent. The systems will be able to support load-reduced DIMM (LR-DIMM) DDR3 main memory, which allows more memory chips to be packed onto a memory stick, 1.25 low-volt memory will also be supported. The new memory controller will have "aggressive power down" and "partial power down" settings as well as memory power capping to keep systems within the thermal envelopes set by administrators. When you add all the memory changes up, Patla says the overall memory performance on the Bulldozer Opterons will be boosted by around 30 per cent.
On the floating point front, the Interlagos chip will be able to 64 flops per cycle on the sixteen-core variant, which Patla estimates will be equivalent to the fastest Sandy Bridge Xeon Intel is expected to field next year. The six-core Xeon 5600s do 24 flops per cycle and there is a less-cored version of Sandy Bridge that will do 32 flops per cycle. The current twelve-core Opteron 6100 chip can do 40 flops per cycle.
With the upgrade to Interlagos being only a chip swap and a BIOS upgrade, Patla is confident that "HPC customers are going to open up the box to do those upgrades." Most enterprise customers don't upgrade their chips but rather replace their servers - with the exception of high-speed trading companies, which can make the cost of such an upgrade back in a short time if it gives them an edge on the stock market.
Those who want Interlagos and Valencia Opterons are going to have to wait a while.
"The product has taped out and we do have early silicon in the labs," said Patla. "We do have partners with silicon and we will be doing mass sampling in the Q4 timeframe. Production is expected to begin in Q2 and we expect to launch and have widespread availability in Q3 2011."
The Interlagos high-end variants of the Bulldozer Opterons will come first, with the Valencia low-end variants in the "high-low" scheme coming 60 to 90 days later.
It would have been more interesting if AMD could get these chips in the field ahead of Intel's Sandy Bridge Xeons, and you have to think that this was, indeed, the plan. You can sure bet that Intel will be trying to jump the gun on AMD with its 22 nanometer processes and the Sandy Bridge Xeons if at all possible. And just to make it interesting, maybe GlobalFoundries, AMD's wafer baker, can do a better job on the 32 nanometer ramp. It will be an interesting summer next year for servers, that's for sure. ®