ISSCC If the Chinese government is scaring the world with its hybrid CPU-GPU clusters, what do you think the reaction will be when Chinese supercomputers shun American-made x64 processors and GPU co-processors and start using their own energy-efficient, MIPS-derived, x86-emulating Godson line of 64-bit processors?
Apoplexy? Disbelief? A polite bow of respect? A bunch of orders for Godson chips is more likely, once you see what China is up to.
One of the more interesting presentations at this week's International Solid-State Circuits Conference, hosted by the IEEE in San Francisco, was by Weiwu Hu, the lead designer of the Godson family of processors being created by Institute of Computing Technology at the Chinese Academy of Sciences.
China started developing its own processor since 2002, explained Hu, and the Godson family of chips, which is based on the MIPS architecture created by Silicon Graphics, is part of a holistic technology investment program. The Godson chip effort is one of 16 different projects, in fact, that are each funded with between $5bn and $10bn.
The massive projects focus on specific technology areas that China reckons are key for its technological independence and economic future, including processors and operating systems, chip process technology, 4G wireless networks, nuclear fission power plants, water pollution control and treatment, aircraft design and construction, high-resolution satellite imaging, and manned spaceflight and lunar exploration.
As El Reg reported a year ago when China's ICT was bragging about its plans to build a petaflops-scale supercomputer with server maker Dawning, ICT originally got access to MIPS technology through its partnership with wafer-baker STMicroelectronics. But in June 2009, as it got serious about its Godson chips (also known by the name Loongson) it licensed the MIPS32 and MIPS64 architectures straight from MIPS Technologies, the chip-designing division of Silicon Graphics that was spun out in an initial public offering in 1998.
The initial Godson-1 processors were 32-bit chips running at a mere 266 MHz, and the Godson-2 moved to 64-bits and was revved up to 1.2 GHz. With the Godson-2F chip in 2007 and 2008, ICT came out with a design that has a four-issue core running at 800 MHz, rated at 3.2 gigaflops. The Godson-3A chip was delayed nearly a year and was aimed solely at servers. ICT shifted a four-core design and also did something else very clever: it added x64 instruction emulation right into the hardware. Hu only alluded to this emulation capability, but as El Reg explained a year ago, the Godson-3 chips have instructions added to help the QEMU hypervisor (the one that's at the heart of Red Hat's KVM hypervisor) to translate instructions from x86 to MIPS format. According to early benchmarks, the emulation penalty is about 30 per cent.
The Godson-3A chip was implemented in a 65 nanometer process and ran at 1 GHz to deliver 16 gigaflops of floating point oomph. The chip has 425 million transistors, an area of 174.5 square millimeters, and burned only 10 watts under load. The chip included two 16-bit HyperTransport ports (licensed from Advanced Micro Devices), 4 MB of L2 cache, and two on-chip memory controllers that support either DDR2 or DDR3 main memory.