ISSCC Intel was not about to pre-announce all the feeds and speeds of its future Xeon and Itanium processors at the IEEE's International Solid-State Circuits Conference in San Francisco this week. But its chip engineers are just like all the others attending the event. They want to show off the electrical engineering marvels they have created, and they did lift a little curtain on future "Sandy Bridge-EP" and "Westmere-EX" Xeon processors, due later this year.
As El Reg previously reported, the chip giant also closed out the enterprise processor sessions at ISSCC with details on the forthcoming "Poulson" Itanium chip, which sports eight completely redesigned cores. So Itanium would not get lost in the shuffle and would get top billing as the press rolled into ISSCC on Sunday, Intel did prebriefings on the Poulson chip last week so the stories would come out ahead of the paper presented by engineer Reid Riedlinger.
The eight-core Poulson chip is the kicker to the current quad-core "Tukwila" Itanium 9300 processor. It was designed by a team of engineers spread across its Fort Collins, Colorado, and Hudson, Massachusetts, facilities, which are obviously historically connected to the chip design teams affiliated with the PA-RISC chips from HP and the Alpha chips from Digital Equipment. Intel borged those teams many years ago in the wake of HP and Compaq/Digital adopting the Itanium chip. The Westmere-EX processor, aimed at high-end servers, was designed at Intel's Bangalore, India, facility, while the Sandy Bridge-EN chip, aimed at entry and midrange servers, was designed by engineers in Santa Clara, California.
Shankar Sawant, an engineer on the Westmere-EX team, presented a paper that generically discussed this Xeon chip, which is socket-compatible with the current "Nehalem-EX" Xeon 6500 and 7500 processors that were announced in March 2010. The Xeon 7500 chip pretty much replaced the Itanium in the affections and server lineups of everyone but HP, which has to continue to use the Itanium to support HP-UX, OpenVMS, and NonStop workloads. The Xeon 6500 are low-powered versions of the Nehalem-EX aimed at HPC clusters with only two processor sockets; the Xeon 7500s and the "Boxboro" chipset shared by Xeon 6500/7500 and Itanium 9300 chips are designed for systems with two, four, or eight sockets.
The Westmere-EX is a tick on the Intel tick-tock rhythm, which means it is a processor shrink on the prior chip design. The Xeon 7500 was implemented using Intel's 45 nanometer processes and had eight cores, each with two virtual threads (what Intel calls HyperThreading) that make it look like sixteen cores to operating systems and hypervisors. The Westmere-EX will be a shrink to 32 nanometers, allowing for more components to be crammed onto the slice of silicon dioxide and for the chip to run faster or cooler at the same clock speed - whatever Intel and its customers think is best. What we know for sure is that Westmere-EX is a ten-core chip with twenty threads.
But if you look at the block diagram for the Westmere-EX, one thing becomes immediately obvious. Take a look:
The cores are numbered and are on the outside, with the "last level cache," which in the Xeon 7600 processors, as the Westmere-EX chips will almost certainly be called, all crammed into the center of the chip. In the dead center of the chip is the QuickPath Interconnect router, and the "uncore" strip that includes this router (the six black squares in the center of the die) splits the chip in two horizontally.