Supercomputer maker Cray has passed another milestone in its research and development effort for the "Cascade" massively parallel supercomputers it is developing for the US Defense Advanced Research Project Agency.
In an 8K filing with the US Securities and Exchange Commission, Cray said that it has taken the next step toward the completion of the Cascade system being created, initially at least, for DARPA. And so, sometime in the first quarter, the company says, the bulk of a $12m payment for the reimbursement of research and development expenses will offset those incurred expenses.
Cray does not book this DARPA Cascade development project as revenue, so it does not affect the top line – but it certainly does help the bottom line. Over the long haul, as Cascade is commercialized (much as the "Red Storm" research system built by Cray for Sandia National Labs was commercialized as the XT and XMT lines), the Cascade machines will directly generate revenues and profits.
In 2010, DARPA paid $36.5m in R&D offsets to Cray for Cascade R&D offsets for three milestones, and Cray said several months ago that it expected to have only two milestones this year, for a total of $24m. The Cascade machines are expected to hit the market sometime around late 2012 or early 2013.
The Cascade system is being created through DARPA's High Productivity Computing Systems program, which gave Cray $250m for Cascade and IBM $244m for the PERCS programming environment that will run on top of its Power7-based supercomputers. (The "Blue Waters" Power7 IH nodes and racks are not PERCS, strictly speaking, but the PERCS environment runs on this iron.)
The Cascade boxes will use a new interconnect, called Aries, a much higher-bandwidth interconnect than the current "Gemini" XE interconnect that replaces HyperTransport links on the ASIC with PCI-Express links. This way, Cray can support both Xeon processors from Intel as well as Opteron processors from Advanced Micro Devices (the latter being the basis of the Red Storm prototype and XT commercial lines).
I know what you are thinking: "Aren't Intel's QuickPath Interconnect and AMD's HyperTransport close enough that Cray should have been able to create an ASIC that could speak to either?" Well, apparently not – but I think Cray could have made it work.
But that's not the issue. DARPA wanted to be able to plug any kind of computing device into a Cascade chassis, including a GPU coprocessor or a field-programmable gate array (FPGA). And that would require a more generic interface, like PCI-Express. As it turns out, DARPA scaled back the Cascade project by $60m in January 2010, and that might have had to do with the integration of some kind of coprocessor for the Cascade systems. Cray never really explained it. ®