IDF 2011 Do you know why Intel hasn't launched the Sandy Bridge-EP Xeon E5 processor for two-socket servers? Neither do we, but after attending Intel Developer Forum last week, we have some pretty good guesses.
Given the relative dearth of processor news at the IDF show, the attendees and vendors that El Reg spoke to at the show had little doubt the Xeon E5 processors were going to be the star of the event. Technically, you can't describe the Xeon E5 as late because Intel didn't give a formal launch date for the chips; it merely said they would be in production sometime this year. And Kirk Skaugen, general manager of Intel's Data Center and Connected Systems group, confirmed last week that Intel is shipping Xeon E5 silicon right now for revenue to selected hyperscale database and supercomputing customers under non-disclosure agreements.
But that is a lawyerly kind of argument. The reality is that the market expected the Xeon E5 last week and Intel to come out swinging to start a new server refresh cycle during the traditional fourth-quarter IT budget uptick.
The motherboard makers are ready and eager, as you might imagine, to start selling aggressively and to be able to talk about the boards they have created that employ the Xeon E5s, which are not socket compatible with the existing Xeon 5500 and 5600 processors. Charles Liang, Super Micro's CEO, said in a conference call back in early August that the company was "pretty much ready to go" with its Xeon E5 boards and systems, that Intel was expected to ship chips in the fourth quarter and, as far as it knew, the launch was on track for Q4 as well.
Why not strike while the iron is hot?
So what caused the E5 delay? First, the Xeon E5 processors sports on-chip PCI Express 3.0 controllers and a new Patsburg C600 chipset. This is the first time that Intel is putting PCI peripheral controllers on chip, and after having had a bug in the Cougar Point C202 and C204 chipsets for the Sandy Bridge-DT Xeon E3 processors back in January of this year, you can bet Intel does not want to repeat this experience – particularly with the workhorse machines that represent the bulk of its server chip shipments and revenues. There has been some chatter that there might be a bug in the PCI Express 3.0 controller in the Xeon E5 chip, but this seems to be just that: idle chatter. An Intel spokesperson gave El Reg an empty stare and said "no comment" when we broached the subject.
We assume that the Xeon E5 chip is working as designed (see our our exposition of the Xeon E5 and C600 chipset from May for details), given that Intel has started shipments to hyperscale web companies and supercomputing clients. Skaugen said in a briefing at IDF last week that the Xeon E5 would be the second most popular processor in terms of shipment numbers in 2011, just behind the Xeon 5600 and ahead of Itaniums, Xeon 7500s, and Xeon E7s at Intel and ahead of whatever Opteron 6100s and 4100s that Advanced Micro Devices can put in the field this year. These are not the kinds of customers you ship a bum product to. So whatever the delay is about, it is not about the chip.
The Xeon E5s - which feature four, six or eight cores per package - are crafted using the 32-nanometer wafer baking processes that were used to pump out Core PC, Xeon E3 and E7 and Xeon 5600 and 7500 chips. There is no big process transition for Intel to cope with here. And with the PC market slowing down and PC chip inventories building up, Intel is not exactly under pressure at its 32nm fabs. That said, the Xeon E5 is probably going to be a relatively fat chip and there could be yield issues that are part of a normal ramp of a new, complex chip.
If you knew you had working Xeon 5600 chips, that companies were still happy to buy them, and they were at the top of their ramp and therefore very profitable, would you shift to a new server chip when you know the PC market could be down in Q3 and Q4 of 2011 and Q1 of 2012? Nope, you would work on the Xeon E5 ramp and get yields up so that when you did launch in the early part of the year you could make more money on them. You would do this particularly if hyperscale and HPC customers, who want and need that integrated PCI Express 3.0 support for its high bandwidth (80Gb/sec into each processor socket), could already buy up whatever inventory you could make in the third and fourth quarter of this year. Intel can not only push out the launch to 2012, but it can push out the launch costs, too.
This is probably all about Intel's profits, as well as those at its server partners.
If the motherboard makers are ready, it is possible that the system makers or the operating system developers are not. Or both. Server makers could need more time to get their platforms ironed out, although it is far more likely that they don't want the disruption of a major product launch in the fourth quarter – something that has not happened to them since 2008, when the Nehalem-EP Xeon 5500 processors were pushed into 2009 because of the Great Recession.
All fired up about Xeon E5
What is clear is that Intel is fired up about the Xeon E5 chip.
"This is the most phenomenal chip out of Intel that we have ever delivered into the server market," Skaugen gushed, adding that the chip giant has over 400 design wins (that's IT vendor speak for unique customer configurations) for machines using the Xeon E5.
This is more than twice as many design wins for the Xeon 5500, which was launched in March 2009 in the belly of the Great Recession to much fanfare and rapid customer adoption because of the vast improvement it offered in performance. Cloud and HPC customers are going to be getting Xeon E5 processors in "extreme volumes" this year, Skaugen said, as these companies are expected to grab 20 times the number of Xeon 5500s they bought two and a half years ago in Xeon E5 processors. That is not just a testament to the stabilization of the global economy and Intel's engineering, but also shows how the chip giant has closed the architectural and performance gap with x64 rival AMD.
"Don't confuse volume shipments under non-disclosure going into the large cloud and HPC customers with when the best time to do a marketing launch is," Skaugen said.
The gauntlet is clearly at the feet of Rory Read, AMD's new CEO who was hired a month ago and has an awful lot riding on the launch of the 16-core Interlagos Opteron 6200 chip - due for launch in the fourth quarter and also already shipping for revenue for the past couple of weeks. ®