You're either on the bus or you're off the bus
One major advance in the P6 architecture was the frontside bus. Before P6, interfaces between processors and the rest of the system were processor-specific. A true system bus, Pawlowski said, understands global addressability and not just processor I/O but system I/O, as well, and offers the opportunity to gang more than one processor and maintain cache coherency.
The P6's frontside bus used Gunning transceiver logic from Xerox, which was able to scale well and and continue to work as voltages declined. "We only thought it would last two generations, maybe two processor generations," Pawlowski said. Instead, it lasted for about a decade.
Another big step for the P6 architecture was out-of-order execution. "It had the reorder buffer," Pawlowski said. "It was able to look at more than three or four instructions at a time. Even if it could only decode and retire maybe three instructions at a time, it was able to have, potentially – gosh, if I remember right – I'm going to say 36 ... instructions that potentially could be in flight at any one time."
The P6's upgrades, he told us, helped that architecture achieve "performance improvements way above what we were getting with Pentium and the superscaler machine."
But perhaps the most radical – and radically effective – improvement in the P6 architecture, and one that helped out-of-order execution as well, was the translation of IA instructions into smaller, more granular micro-operations, or µops, which were more easily dispatched through the P6's out-of-order, superscalar architecture.
As Pawlowski told us, "As I keep telling people today, 'We really do binary translation in hardware in these machines'." The beauty part of binary translation, he said, is that such binary translation to µops can work with different architectures while still keeping full IA compatibility.
"You've got the flexibility of changing the underlying machine," he said, and then rattled off some of those changes. "Every process generation and processor generation, we add better branch prediction, we may add different functional units like the trace cache that was added on Willamette [the first Pentium 4] ... larger vector units, adding a vector unit with AVX and then continuing to extend that, looking at ways to elide locks and make your locks faster but still maintain the semantics of locks because that's what programmers still use, but try to get the speed and limit the impact of contention so that we can just continually improve the processor performance."
All of those changes are more easily accomplished, Pawlowski said, in a processor that has full binary translation – and that's one of the things that the P6 brought to the party.
P6 lasted for three generations – the Pentium Pro, Pentium II, and Pentium III – but it was to make a comeback.