Coming soon to an Intel chip near you...
Borkar, Faggin, and Bohr all agree that it was about a decade ago when it became clear that pure Dennard scaling wasn't going to cut it.
As we pointed out when celebrating the 4004's 40th birthday earlier this month, the first major process-technology innovation was strained silicon, which increased electron mobility while tamping down current leakage. Intel's first strained silicon processor was the "Prescott" Pentium 4 of 2004.
After strained silicon came high-k metal gate technology, which debuted with Intel's 45nm process in 2007. This advance added a better-insulating gate oxide and a metal gate to further reduce leakage and improve performance.
Next up is what Intel calls "3D" or "tri-gate" transistor technology, in which the channel doesn't lie flat, but instead sticks up into the gate, offering a larger channel surface area in a smaller geometry. Tri-gate transistors will be first used in Intel's 22nm "Ivy Bridge" chips, scheduled to ship next year.
But that increased surface is not the best thing about tri-gate, Bohr told us. "There is a benefit from an increased channel area, but it's not the big one," he said. "The big benefit is that as you are forming the transistor on a narrow, vertical silicon fin, or pillar, the electrostatics are improved – the gate electrode has better control of the channel area. The result is a device that's called 'fully depleted'."
If you're having trouble undersanding why that's important, the answer is really rather straightforward: the big advantage of a fully depleted transistor design is that it has a steeper sub-threshold slope – which means, essentially, that since the transistor's on-current versus off-current characteristics are improved, the transistor can have a higher on-current when it's switched on, improving performance, and a lower off-current when it's switched off, reducing power leakage.
Pawlowski – being a microarchitect and not a process technologist, has nothing but admiration for the engineers who create the silicon upon which his designs run. "The process guys are phenomenal. They really are," he told us. Referring to how the "process guys" manage to remain on a cadence of every 18 months to two years to bring out new process technologies, he said, "They're a machine."
Pawlowski doesn't see that cadence stumbling anytime soon. "I see them scaling to sub-10 nanometers well into 2020, 2022," he said. "And it's going to be our challenge of being able to use the transistors that are given us in a more efficient fashion."
That decade-or-so prediction is about right, thinks Borkar. "We're very confident that for the next 10 years, there is Moore's Law, there's no doubt about it," he said. "After that it's hazy.
Faggin extended Brokar's estimate to 20 years. "The mainstream for the next 10, 20 years is more of the same: faster processor, more cores, blah, blah, blah – all this stuff that we have been doing for the last 40 years," he said.
But the future is always hazy, Borkar says. "Ten years ago if you had asked me that, I would have said that."
But there are parts of that haze that are less hazy than others, Fagin says. "There are new things appearing at the horizon. First of all, we are beginning to come to the end of the road in terms of reducing the physical size of transistors. And so we have to find new ways of actually building these things – new materials to use, and so on."
Materials-man Bohr has some ideas as to what those materials might be – namely what are called III-V materials such as gallium arsinide and indium phosphide, which are given those Roman-numeral designations to indicate the number of their "valence electrons", the electrons in the outer shell of an atom that govern that element's interaction with other elements.
As Intel marches its process size down to 14nm, then 10nm, then 7nm, Bohr says, one area of investigation will be on using III-V materials to coat the silicon substrate. III-V materials will provide higher electron mobility, thus allowing transistors created in this way to be operated at lower voltages and lower leakages.
But Bohr emphasized to us that silicon will still be the core material in play. "Please don't have the mistaken impression that we will be changing from silicon wafers to gallium arsinide wafers," he said. "That's not what we will do. What we will do is stay with a silicon wafer, and then deposit some very thin layers on top of that wafer that are these special III-V materials."
Such a relatively straightforward coating process would have the added benefit of keeping incremental costs-per-chip low. "So it's not going to be a major cost increase," he said – but then added: "But it will increase somewhat the cost and complexity of what we do, but that's kind of name of the game for the past ten years."
Transistor structures might change, as well, as they have with Intel's tri-gate technology. But as to what those changes might be, no one was talking. "There are lots of thiings on the drawing board," Borkar said. "It is not very clear what the winner is. It's real early."
Bohr agreed. "We are clearly in an era now where we have to be almost continually changing, improving, inventing new materials and new transistor structures. I think you'll see more of that in coming generations."