An impressively staffed startup by the name of SuVolta has teamed up with Japanese heavyweight Fujitsu Semiconductor to create a new chip-baking technique that promises low-power, inexpensive chips created in a highly scalable process and manufactured using equipment that's already ready in chip foundries.
Yes, that description is a bit of a mouthful – but that's the breadth of promise offered by SuVolta's "deeply depleted channel" (DDC) CMOS transistor tech, as presented on Wednesday by a Fujitsu researcher at the 2011 International Electron Devices Meeting (IEDM) currently underway in Washington DC.
If DDC works as advertised – and from the deep-dive details and test results provided to The Reg by SuVolta's director of device and modeling Lucian Shifren, we have no reason to think that it shouldn't – it could revolutionize how low-power system-on-chip (SoC) silicon is created.
What DDC involves, and what provides its promise, is a new way of creating transistors based on standard bulk planar CMOS manufacturing techniques, and not on more-expensive and specialized transistor manufacturing processes that have cropped up in the past decade or so to allow chip designers to keep pace with that tough taskmaster, Moore's Law.
Shifren emphasized that although DDC could be applied to any level of chippery, SuVolta is currently more concerned with foundry-created, low-power chips, and not the hefty x86 CPUs baked by Intel in their custom fabs. SoCs are where the market is headed, he told us.
"CPUs and GPUs are not actually driving the semiconductor market anymore," Shifren said. "What's driving it are SoCs, and especially those adapted to mobile forms."
The company that's currently driving semiconductor technology, however, is Intel. But Chipzilla has traditionally focused its research on larger, more powerful chips based on the aging IA architecture – although it would dearly love to break into the lucrative mobile market, dominated by non-IA ARM chippery.
"If you look at the industry as a whole right now, who really defines the technology and the technology roadmap?" Shifren asked, rhetorically. "It's Intel." He also gave historical props to IBM, but averred that in recent years Intel has been leading the way.
As an example, Shifren offered Intel's variation of 3D FinFET transistor technology, what Chipzilla calls Tri-Gate. "Have a look at how after Intel made its announcement of FinFET, everybody and their mother came out and said they were going to be working on FinFET," he said.
According to Shifren, however, neither FinFET nor another transistor structure known as fully depleted silicon-on-insulator (FD-SOI), which has been around for nearly a decade, are the best choices for the low-power, low-cost SoC market – although others may disagree when Shifren says "I believe FD-SOI is dead."
SuVolta's DDC transistor shares many advantages of cheap-as-dirt, versatile bulk planar CMOS (click to enlarge)
Not only are both of those techniques expensive when compared with good ol' traditional non-depleted planar bulk CMOS, Shifren says, but they don't scale well for creating a range of chips running at different voltages.
(A bit of background: you'll notice that the term "depleted" is being bandied about a bit. Simply put, a depleted transistor is one in which stray current is minimized in such a way as to prevent power leakage, and to allow the transistor to be activated at a lower voltage. For a fuller explanation, check out an earlier Reg article about Intel's tri-gate transistors.)
Shifren told us that voltage reduction has been given short shrift in the drive to keep up with Moore's Law. "If you look at Moore's Law, and how Moore's Law has been evolving over the last couple of years," he said, "advances in patterning and moving to double patterning, immersion masks, and things like that, the industry has been able to keep along with Moore's Law – as long as you're talking about dimensional scaling.
"But if you have a look at the voltages," he continued, "they haven't scaled nearly as quickly. They actually haven't scaled at all in the last couple of years."
He recited the history of processor voltage scaling, starting a five volts, then down to the low fours, then 3.5V, 2.5V, 1.8V. Then curve of the decreases began to flatten out, now hovering around 1V to 0.7V. Moore's Law, on the other hand, has kept chugging along, doubling transistor density every 18 to 24 months.
SuVolta's breakthrough is that it has managed to slash that voltage requirement essentially in half, a level of improvement that should please any fan of Moore's Law–scale improvements. The company's DDC transistors, used in a proof-of-concept SRAM chip manufactured by Fujitsu, require a mere 0.425V.