Updated Upstart multicore RISC chip maker Tilera is timing the launch of its third generation of Tile processors to rain a little on Intel's forthcoming parade, and to try to blunt all of the excitement that is building for ARM-based alternatives for servers.
Tilera will today begin sampling of its Tile-Gx series of processors. As El Reg suspected back in June 2011 - when Tilera announced it was actually launching three different lines of Tile-Gx chips: Gx3000s for servers, Gx5000s for heavy media processing, and Gx8000s for network equipment makers – all three lines are based on Gx8000 chips with certain features deprecated and different pricing.
That means Tilera can offer variants of the chips with 16, 36, 64, and 100 cores and only have to do four chip layouts instead of as many as a dozen. It is the full-on Tile Gx8000 chips with 16 and 36 cores that are in fact sampling now at 1.2GHz, Bob Doud, director of marketing at the upstart chippery, tells El Reg.
A Tilera GX chip wafer, etched by TSMC in 40 nanometers
All three generations of Tilera processors have the same idea behind them: use simple RISC cores tuned for Linux infrastructure workloads, put lots of them on a chip, and link them together using an on-chip a mesh network that makes all of those cores look like a single, monster, multithreaded processor to the Linux kernel.
The big change with the Tile-Gx family is that Tilera is moving from 90 nanometer wafer baking processes from foundry partner Taiwan Semiconductor Manufacturing Corp (used with the two prior Tile generations) to the same 40 nanometer processes used by AMD and Nvidia for their GPUs and by Oracle for its Sparc T4 RISC processors.
As part of the process shrink, Tilera is stepping up to 64-bit processing and 40-bit physical memory addressing, which means it can put 1TB of memory on the single socket processor. A few of the models have 39-bits, which mean they can only address 512GB. The Tile-Gx chips include on-chip DDR3 main memory controllers as well as virtual networking and encryption acceleration units (the latter only in the Gx8000 series).
Here's how the Tile-Gx 3000 server processors stack up against the Tile-Gx 8000 network processors:
Tilera's Gx3000 and Gx8000 processors
There have been some changes to the expected chip lineup since last June. The Gx3000s will now be available in 1GHz and 1.2GHz clock speeds, not the faster 1.5GHz speeds, to keep the thermal envelope down. The two top bin Gx3000s will have three PCI-Express 2.0 slots running at x8 lanes, not a mix of x8 and x4 lanes. Tilera is also adding 1.2GHz options for the top-bin Gx8000 chips.
Tilera does not do SMP to increase the performance of a server node, but rather uses the on-chip mesh to build a bigger socket image with more physical threads.
Each core on the new Tile-Gx chip has three instruction threads and has 32KB of L1 data cache and 32KB of L1 instruction cache, and also has a 256KB L2 cache; the mesh network is used to link those L1 and L2 caches into a single, coherent L3 cache shared by all the cores on the chip - so the top-end, 100-core variant of the Tile-Gx chip has 32MB of total cache.
Tilera Tile-Gx block diagram
The Tile-Gx also has math instructions that allow a floating point operating to be done in five cycles instead of hundreds of cycles when done in software, and believe it or not, this is important for some hyperscale Web applications built using PHP.
Doud says that the ramp for the Tilera chips has been pretty steep, with over 80 engagements with system and network equipment vendors of all colors and stripes, and 20 design wins where the company has committed to use a Tile processor. Embedded system maker Mercury Computer and video streaming equipment maker Harmonic have gone public admitting that they are using Tile chips in their gear.