Motorola is preparing a next-generation two-core G4-class PowerPC processor, the company will this week tell attendees of its annual Smart Networks Developer Conference, held in Disneyland Paris.
The chip, as yet unnamed - at least in public - will contain two PowerPC cores with AltiVec, Motorola's SIMD engine. It will also contain its own memory controller, capable of connecting to DDR and DDR 2 SDRAM, according to documents seen by The Register.
It will interface with the rest of the system using Rapid IO, the next-generation chip-to-chip bus developed by Motorola, but offered as a standard to the embedded processor industry. Given Motorola's Rapid IO heritage, support for the bus isn't surprising - indeed, on sales collateral produced earlier this year, the company's roadmap features a new chip, called the G4+, with Rapid IO built in.
However, the chip will also support "general purpose IO" - presumably a reference to the 745x family's current bus, MPX - so the processor is clearly being designed with backward compatibility in mind.
The G4+ that appears on the January roadmap will be fabbed at 0.1 micron, the sales sheet says, and will feature a "higher level of integration" than previous G4-class CPUs. As of January, the G4+ was simply a proposal to Motorola chiefs, but from presentations Motorola will make this week at SNDF, that the chip has been given the green light.
As one presentation says: "We are putting a dual core PowerPC on our roadmap," and that a "high performance dual core is on our roadmap in a manufacturing process that provides a cost-effective solution." That suggests a 100nm as per the G4+ or, more likely, 90nm process.
The chip is some way off, with a 2004 appearance at the earliest. Motorola's roadmap shows the company will split the G4 family next year into two lines: one featuring "integrated" parts, the other "discrete" chips. So Motorola still sees the value in offering straightforward processors without the extra IO and memory manager functionality.
Whether that's because it still sees Apple as a potential customer isn't known.
The dual-core processor is said to be "capable of going up to 2GHz" with 25W of power dissipation at 1.5GHz. By contrast, the upcoming 7457 dissipates 30W at 1.4GHz. Those are Motorola' numbers, based on a 7457 with a 1.6V core voltage. Motorola's dual-core presentation doesn't give a core voltage, but it's likely to be around the 1.6V mark.
Apple watchers dismissive of that 2GHz target should bear in mind that Motorola's SNDF event targets the embedded market, the focus of the company's sales efforts. Motorola supplies Apple 1.25GHz and 1.4GHz 7455 processors - with part numbers like XC7455ARX1250PF and XPC7455BRX1400PF, respectively - but officially the 7455 only goes up to 1GHz.
The 7457 officially maxes out at 1.3GHz, but that's a frequency intended to appeal to embedded processor makers. The version offered to Apple is likely to clock much higher, though whether Apple takes it or not is another matter - it may prefer IBM's 64-bit PowerPC 970.
The bottom line is that Motorola almost certainly can offer significantly higher clock speeds to its desktop customers, even though it doesn't generally discuss such products, presumably to indicate its strong focus on the embedded market.
That applies as much to future dual-core parts as to today's G4-class CPUs, and Motorola believes it can offer such a chip at high clock speeds yet keep it within today's chips' power dissipation levels.
Achieving that will be Motorola's 90nm silicon-on-insulator (SOI) fabrication process (HiPerMOS 8-SOI) and the company's use of low-k dielectric materials, as we reported yesterday. HiPerMOS 8-SOI is due to come on stream early next year. Beyond that, during 2005, Motorola will transition to HiPerMOS 9-SOI, its 65nm process, which also pulls in thin-film SOI techniques. AMD is working with IBM on something similar (see AMD 'super' SOI to boost chip speeds by 30%). ®