Current technology should serve chip bakers well through the 14-nanometer process node, but if transistor scaling is to shrink further, a number of different possible avenues need to be explored.
Brand's talk focussed mainly on the materials challenges of scaling CMOS transistors beyond the 14 nanometer node, but he also gave an interesting peek into the future structures that those transistors might employ to get down to nodes as small as 3nm.
Planar – "flat", essentially – transistors enabled significant scaling reductions until recently, Brand said, but at around the 45nm node the transistor gate length (Lg, or Lgate) essentially hit a wall due to a number of different causes including electrostatic scaling problems and the degradation of drain-induced barrier loading (DIBL).
If those terms are unfamiliar to you, don't fret. All you need to know is that conventional transistors wouldn't scale down any further, and new approaches were needed. The solutions, he said, were thin channel devices such as FinFET and ultrathin-bodied silicon-on-insulator (SOI) transistors.
DRAM inventor Robert Dennard also developed the theory behind semiconductor scaling (click to enlarge)
FinFETs, as we've explained previously when discussing Intel's "Tri-Gate" implementation, is geek speak for a vertical "fin" of silicon poking up into a the gate of a field-effect transistor, aka a FET. These "3D" transistors are all the rage among chip designers these days – but they, also, will hit the wall in the foreseeable future.
According to Brand, fin widths can be scaled down to about the 5nm level, which means that FinFETs can be scaled down to about a 10nm gate length, "because generally you want to have the gate length about twice the fin width."
Around that 10nm node, however, a new fin material will be needed, such as silicon germanium (SiGe) or possibly just germanium, since the latter has simpler cleaning and higher electron mobility, Brand said.
"Beyond that," he said, "there's many different pathways that the industry could take." One would be to use what's call a gate-all-around (GAA) structure, in which – as its name suggests – the gate wraps around the entire fin. (Which, of course, is no longer a fin, per se, but you get the point.)
Another choice might be using III-V compound materials for the fins, so named because those materials contain three or five electrons in their outer, or valence, shells. Promising semiconductor materials of this type include gallium arsenide (GaAs) and indium gallium arsenide (InGaAs).
The final structure that Brand described is the tunneling field effect transistor (TFET), which would allow even lower-voltage operation than other solutions.
As mentioned above, the bulk of Brand's presentation, "Precision Materials to Meet Scaling Challenges Beyond 14nm", discussed the materials and manufacturing challenges that will come as chip bakers attempt to progress beyond the 14nm node. Unfortunately, much of it went sailing far over the head of your Reg reporter, but you can find more information in the abstract of his talk.
But the take-away from that abstract is straightforward: "To continue logic scaling at 14nm and beyond, structure enhancement and improved materials are needed." ®