SMC Micron has revealed some of the goals – and the manufacturing challenges it faces – for the development of its next-generation "all silicon" Hybrid Memory Cube (HMC).
Micron's current HMC Gen2, engineering samples of which having been released this September, stacks up layers of memory cells, each on an organic laminate substrate, into a 3D structure connected by through-silicon vias (TSVs).
"We're migrating into a chip-scale package where we eliminate the substrates, basically the laminates that we are familiar with," Micron's advanced packaging R&D man Michael Koopmans told attendees of this week's Strategic Materials Conference in Santa Clara, California.
"That transitions us from a typical package-level with organic substrates into a chip-scale package where we only have a silicon cube," Koopmans said. Also in development is a refinement of this chip-scale package that he referred to as a "wide I/O cube that's just a bare cube of silicon with very high-density interconnects between the die and the bottom of the die."
Micron's HMC effort, he said, is moving towards an "all-silicon future." The reasons for the move include the desire to remove those laminate substrates to allow for smaller dimensions. In additional, power requirements will also drop because signals won't have as far to travel through the TSVs.
"Last but not least," he said, "we can eliminate quite a bit of packaging costs and materials. Substrates – these run 10 layers, 12 layers and up – they are not inexpensive." He noted that although wafer-material costs are going down with economies of scale, packaging materials are getting more expensive as requirements for them become more stringent.
And so Micron plans to dump those expensive organic laminate substrates and replace them with silicon or organic interposers – essentially separators rather than structural laminate floors for each level of the 3D structure.
Manufacturing challenges, however, abound. "All-silicon cubes are not simple," Koopmans said. One obvious challenge is that with higher pin counts and increased densities and TSVs, everything gets tighter and the silicon gets thinner per element – and the thinner that silicon gets, the more susceptible it is to warpage, especially when only one side of it is bonded with metal.
The vertical "pillars" through which the TSVs run get closer together as the densities of the rest of the memory cube tightens up. "We're already talking about thousands of pillars on an HMC cube, and many thousands of interconnects," Koopmans said. "I don't think there's a good answer on how tight is everything going to go, but for Wide I/O, for example, we're already down in 40-micron interconnect pitch – so it keeps scaling down and down and down."
Forty microns will seem spacious in the future, however, according to Koopmans, as interconnect pitches will soon shrink down to 20 microns, "and probably lower in the future." And as you might assume, the smaller the interconnect pitches, the more insanely accurate layer-stacking and package-assembly equipment must become.
There are many other manufacturing and material challenges, but Koopmans focused on one in particular – after all, he only had about a half hour for his presentation – and that was the liner needed to insulate the copper TSVs from the silicon through which they pass.
The HMC Gen3 cubes will have multiple thousands of TSVs, and as we mentioned above, they're getting smaller and more densely packed. Despite this shrinkage, the liner must be as thick on the top as it is on the bottom of the pillar, and must be deposited both thoroughly and evenly throughout the pillar. Not a simple feat – but if even a fraction of the pillar is not so coated, current will run from the TSV into the silicon where it's not wanted, and the copper of the TSV will diffuse into the silicon, creating copper silicide (Cu5Si), with disastrous results for the pillar.
If these and other manufacturing challenges are met, there's still the matter of protecting the cube itself. "You want to ship these cubes across the world," Koopmans said, "you want to send them into tests, you want to put them in a socket and test them – something got to go around these cubes."
Micron plans to use wafer-level encapsulation, which Koopmans said is "very much used in the industry" for chip-scale packages, but they haven't yet decided what material to use for that process. "Since we use 300-millimeter wafers, we want to make sure we get a material that is very easily applied on 300-millimeter wafers, either in a granular material or a liquid."
The material they choose needs to have high thermal conductivity, because they want it to help draw heat from the multiple layers of the cube. Also, Koopmans has ruled out high- or even moderate-stress materials for his fragile wafers. "They shrink," he said, "and your wafer turns into a potato chip."
Bottom line: as clever as any HMC Gen3 device design may be, "It's got to be manufacturable," Koopmans said. "Doing the R&D is one thing, having it manufacturable where we can address assembly issues, test issues – it all relates to yield, and of course cost."
It always all comes down to cost, doesn't it? ®