DRAM and flash fabber SK Hynix is set to mass produce 3D NAND by the end of this year, while Micron Technology sees its own 3D mass production kicking in during the second half of 2015.
By building NAND chips with layers of current planar cells (known as 2D NAND) the amount of capacity in a chip's footprint can be raised without needing to go to smaller flash cell geometries.
With smaller cell sizes, its working life (endurance) goes down while its error rate goes up. SanDisk has just announced a 15nm process (1Z), moving down from the 19nm (1X) size used by it and its fab partner Toshiba.
Samsung has SSDs available using 19nm technology. SK Hynix began full-scale production of 16nm flash chips at the end of 2013.
Micron expects to have a 16nm SSD in the first half of this year. This can keep it going on the capacity raising front but it seems unlikely that it, and the industry will move to sub-15nm cell sizes because of these scaling-related problems.
That means its ability to increase planar chip capacity without increasing the chip's footprint size will come to an end, and so 3D NAND, with stacked planar layers, is seen as the answer to increasing capacity requirements until some denser 2D post-NAND technology becomes available.
Think of 3D flash cells as being like condos – blocks of apartments in a housing estate – with planar cells being single-storey dwellings. You can house more people in a fixed estate area using 4-storey condos than you can with single storey homes.
Hypothetically, if a 128Gbit planar chip is possible with 16nm NAND while, say, only 64Gbit is available with 19nm NAND, a 4 layer 19nm chip could provide 256Gbits. That's twice the capacity of the planar 16nm chip but within the same footprint. An 8-layer, 19nm 3D chip could provide 512Gbits, trouncing the 16nm planar cell's 128Gbit capacity.
A 4-layer, 16nm cell chip could provide 512Gbit capacity and an 8-layer chip 1,024 Gbits, making for lots of decent selling conversations between NAND chip reps and tablet/mobile phone suppliers.
It's not going to be as simple as this because vertical tunnels between the layers are needed to connect them to a base layer of logic circuitry. These connecting holes, Through-Silicon Vias (TSVs), use up some of each chip layer's area. The more layers you have, the more TSVs you need, thus (we understand) you need more logic in the base layer. Consequently the production and testing process becomes more and more complicated.
SK Hynix began full-scale production of 16nm flash in June, 2012, and moved to a 2nd gen process at the end of 2013. If it can get the number of layers high enough in its coming 3D chips then it could gain a significant capacity advantage over its competitors' planar chips.
The company is also aiming to introduce its own flash controllers and produce 3-layer cell (TLC) NAND using its 16nm technology. ®
Thanks to Stifel Nicolaus MD Aaron Rakers whose report on Hynix' results formed the basis for this article.