Resistance is not futile: Here's a cookie sheet of luke-warm RRAM that proves it

Look, ma - no edge structure!


Boffins devising Resistive RAM (RRAM) have found that using porous silicon oxide makes the devices easier to manufacture, longer lasting and less power hungry.

The researchers, at Rice University, Texas, stumbled upon silicon oxide RRAM five years ago. The stuff works as computer storage by having differing resistance levels signify binary digits. Previously, graphite was thought to be the best RRAM material.

RRAM bridges the gap between NAND and DRAM by offering faster speeds than NAND while being non-volatile, as well as having DRAM word-level addressability instead of NAND's block addressability.

Rice's RRAM involves a nanoscale channel or hole in a sheet of dielectric (that is, non-electrically conductive) silicon oxide, which is sandwiched between layers of conducting material. Applying a high-enough voltage to the silicon oxide creates a conductive path between the two layers sandwiching it. Turning off the current breaks the path – meaning the technique can be used to store binary 1s and 0s.

The latest Rice announcement talks of “the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires” and schematic diagrams show what they mean:

Rice_RRAM_Schematic

Scanning electron microscope image and schematic showing the design and composition of RRAM memory devices based on porous silicon oxide. Credit: Tour Group/Rice University.

Rice_RRAM_wire

Schematic picture of the rewriteable crystalline filament pathway in Rice University's porous silicon oxide RRAM memory devices. Credit: Tour Group/Rice University.

By using porous silicon oxide the boffins say that their RRAM memory can be manufactured at room temperature and doesn’t need a device edge structure. Explaining what this means, Rice boffin bunch boss James Tour says: “That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges."

He continues: "When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

The much-titled Tour is Rice’s T.T. and W.F. Chao Chair in Chemistry, professor of mechanical engineering and nanoengineering, and of computer science.

Porous silicon oxide RRAM only needs a 1.6 volt charge to form the conduction pathway; that's a 13-fold improvement over the team's previous best, and, in their words, “a number that stacks up against competing RRAM technologies.”

Tour said: “Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory. It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

Suppliers such as Crossbar are working to develop RRAM products, as is HP if the memristor is classed as a resistive RAM product.

Tour said Rice had already been approached by companies wanting to license the technology.

The full study is titled Nanoporous Silicon Oxide Memory by Gunuk Wang, Yang Yang, Jae-Hwang Lee, Vera Abramova, Huilong Fei, Gedeng Ruan, Edwin L. Thomas, and James M. Tour. Nano Lett., Article ASAP DOI: 10.1021/nl501803s, dated July 3, 2014, and can be read online here. ®


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