Is that a 64-bit ARM Warrior in your pocket? No, it's MIPS64

Use your Imagination: When two tribes go to war

Chip designer Imagination Technologies today went public about its new processor design – the 64-bit MIPS Warrior I6400.

It's an ambitious blueprint, aimed at car dashboards, digital TVs and tablets – the usual space for Imagination – all the way up to data center-grade compute, storage and networking kit. In other words, wherever arch-rival ARM is attempting to spread its limbs.

The I6400 CPU is pretty much a MIPS64-friendly version of the 32-bit Warrior P5600 that was talked up last fall, with a few extra features thrown in.

For example, the I6400 has the simultaneous multithreading (SMT) seen in Imagination's 32-bit Meta system-on-chip family: this technology essentially turns each physical core into two or four virtual cores. A hardware scheduler interleaves the virtual CPU threads into the processor's execution queues, the meat grinders of the chip.

You may better know SMT as Hyper-Threading, which is what Intel calls its implementation of the technology. The idea is to maximise performance, by cleverly scheduling instructions so the processor is always working, without sucking up too much power. Imagination reckons splitting a physical I6400 core into two hardware threads will increase its physical footprint by about 10 per cent while boosting performance by 30 to 60 per cent.

The I6400 can handle up to six physical cores coherently per cluster – that’s Imagination’s term for a block of cores on a system-on-chip rather than a cluster of machines – and up to 64 clusters per node, if you want to go crazy.

It also has a 128-bit SIMD unit and hardware virtualization support, just like the P5600. The hardware virtualization works by assigning virtualized guest operating systems and bare-metal apps a four-bit-wide ID number – 1 to 15, 0 is reserved for the hypervisor – and then exposing that ID number to the rest of the system-on-chip hardware. (Imagination tells The Reg that there's nothing stopping it widening that number later on.)

Click to enlarge

So, if (say) guest/app ID 3 accesses some part of the system memory map, that ID number is embedded in the bus transaction – allowing peripherals to ignore or abort the access if that program shouldn't be touching that particular part of the computer.

If guest/app ID 3 is supposed to be running the networking stack, there's no need for it to directly touch the onboard sensor registers, let's say. This mechanism, as an alternative to classic page table management, introduces a firewall, if you will, between the various software components in your embedded gadget – but as with ARM's TrustZone and Intel's SMM, hardware separation is not totally infallible where buggy software is involved.

Instruction set argument

The key difference between the I6400 and the P5600, though, is that the former can run MIPS32 and MIPS64 code, whereas the latter was MIPS32 only – making the I6400 the first 64-bit Warrior processor. Imagination could not stress hard enough to your humble hack that the MIPS64 instruction set is an extension to MIPS32, rather than a replacement.

Where rival ARM's shift from 32-bit ARMv7 to 64-bit ARMv8-a involved rewriting chunks of its instruction set and forcing some low-level engineers to learn a new assembly language, MIPS64 is basically MIPS32 with instructions for using 64-bit-wide data, and it runs MIPS32 code without a mode switch.

Imagination, best known for its PowerVR graphics cores in iPads and other things, hopes this means people won't find it a chore picking up MIPS64 if they already know MIPS32. Bear in mind, MIPS64 has been around since 1999.

Specifically, the I6400 implements MIPS64 release 6, for which the documentation is available. Imagination claims r6 includes "additional instructions for enhanced execution on modern software workloads" –for example: position-independent code, just-in-time engines and virtual machines. El Reg is still perusing the docs; we’ll delve into release five versus six shortly.

Ironically, MIPS and the new ARMv8-a (PDF) instruction sets are conveniently similar: for instance, they both have a fixed register that always contains a zero value, they both have tons of general purpose registers, each instruction is the same width, the program counter is not directly accessible, and so on.

So if you can master MIPS64, you can master ARMv8-a, and vice versa. It should be said that both ARM and Imagination are keeping hold of their power-sipping 32-bit architectures, particularly towards the low-end of the battery-powered embedded computing world. It’s their bread and butter. But it’s clear the pair are now both brandishing 64-bit RISC designs for multi-core smartphones and tablets, and data center hardware.

With 64-bit, you get more headroom with your virtual address space – Warriors cores have been able to address up to 1TB of physical RAM for a while now – as well as cleaner and faster manipulation of 64-bit data. That larger virtual address space is handy for running big applications or modern guest OSes in a hypervisor, which is right up server street. Imagination hinted in August last year that a 64-bit Warrior was due around about now.

Put yourself in Imagination’s shoes: in 2012, the graphics core designer bought the MIPS technology for $100m, giving it a long-standing 32-bit and 64-bit compute architecture – an architecture found in the original Sony PlayStation, countless home routers and entertainment devices, and other gear.

”We didn't acquire MIPS for the hell of it,“ Imagination CEO Hossein Yassaie quipped to reporters last year. The move put Imagination in the path of embedded processor design stalwart ARM, which was working on its own 64-bit instruction set for servers and smartphones – one that shares features with MIPS64 but the underlying electronics are, of course, vastly different.

“It’s flattering,” Mark Throndson, Imagination’s director of processor marketing and business development, told The Register a few days ago when pushed about the similarities of the MIPS64-ARMv8 languages.

“With 64-bit ARMv8, there are differences, but they do say copying is the sincerest form for flattery. [32-bit] ARMv7 and [64-bit] v8 are also quite different; that’s not something that you get with MIPS. MIPS64 is an extension of MIPS32, and it’s already been on the market for 20 years.”

Click to enlarge

A base configuration of the I6400, manufactured by TSMC, has four cores – with two SMT threads per core – plus 32KB data/instruction L1 caches, a 1MB L2 cache, and each core takes up a millimetre square of silicon. The design is licensed to chipmakers, who should have packages available by the end of the year – just in time to go head to head with AMD's beefy Seattle 64-bit ARM system-on-chip.

If you can't wait that long, the prpl foundation has crafted a QEMU port supporting MIPS r6 here, although you'll need to obtain an r6-capable toolchain to make use of the updated instruction set.

If MIPS32 is more your thing, there's a new Creator CI20 dev board powered by a 1.2GHz Ingenic JZ4780 system-on-chip.

Meanwhile, a port of the upcoming Android L operating system to MIPS64 r6 is also in the works, we're told. ®

Similar topics

Other stories you might like

Biting the hand that feeds IT © 1998–2022