Ethernet silicon vendor Xpliant – currently being digested by Cavium in an acquisition due to conclude in 2015 – is hoping to knock Broadcom out of its spot at the heart of the Ethernet switch market.
The upstart, launched in 2011, says it'll have sample silicon in Q4 2014 for an architecture designed to combine speed and programmability.
The Xpliant chips were, according to the company's Dan Tuchler, designed to scratch an itch that its developers had experienced as chip designers in other companies: “Every year, they did the same thing over again: a little faster, a couple more features, but pretty much the same architecture”, they said.
That leaves end users of Ethernet switches in the position of having to rely on the features supported in the current chip. “If you're an end user and you just installed 200 Ethernet switches and you want a new feature, you'll have to scrap 200 switches or go without the feature”.
The opportunity Xpliant is trying to address is one in which the chip can be revised with software upgrades. The XPA – Xpliant Packet Architecture – puts switching logic on the chips “in which every parameter can be configured very quickly”, he said, so “you can add different protocols to [finished devices] via a software update”.
Why would users bother? Tuchler said the growth of data centres and the parallel growth of the virtualisation market provides a good example of the opportunity. A data centre switch built before VMWare's VXLAN protocol isn't ready for virtualisation; one that only supports VXLAN isn't any good if the data centre operator wants to add support for Microsoft's NVGRE; he has to run the forklift upgrade again, and then, if the IETF's GENEVE RFC gets adopted, yet another bunch of switches have to be ditched.
In current merchant silicon, such protocols – along with how addresses and statistics are handled – are hard-coded. By making its silicon more programmable, Tuchler said, “if you want to do a different kind of table lookup or support a new protocol, you can. You can configure every stage of the switch – you write software, and push it out to the switch”.
That programmability, he added, also means that the same hardware could be configured in software for either “spine” or “leaf” applications in a data centre: a switch could be tuned to allocate buffers differently for different positions, he said; different protocols are more important in the leaf or the spine; or the mix of port speeds could be adjusted to the different application.
“Depending on our customers' strategy we can enable different port speeds: the leaf would have maybe lots of downlinks at 10 Gbps and the spine would have lots of mesh nodes at 100 Gbps,” he said. A manufacture could make their switches support that kind of reconfiguration “with a code load.”
The company also hopes that Ethernet switch OEMs will bite on the idea that they're no longer going to be constrained by the silicon they buy to produce what ends up being largely generic hardware, differentiated only by things like management.
OEMs can get the chance to “innovate at the data plane again”, he said – “what protocols are processed, how they're processed.”
There are four flavours in the XPA-architecture chip planned: 880 Gbps, 1.28 Tbps, 1.76 Tbps, and 3.2 Tbps. Sampling of the chips starts in Q4, along with eval boards to help designers get moving. Those raw speeds can be sliced and diced in various ways, to support configs between 128 x 10 Gbps Ethernet ports up to 32 x 100 Gbps Ethernet ports.
The chip supports the emerging 25 / 50 Gbps Ethernet offering championed by Google, with what the company says is a standard API that will be familiar to designers working with it.
For OEMs that want to get moving now, there's an SDK available now, along with a “white model” of the chip providing access to the chip's features, running on Windows or Linux, and an FPGA-based “cycle-accurate” hardware simulator. ®