The first volley in the volume x64 server price war was officially fired today, with Intel rolling out its "Westmere-EP" Xeon 5600 processor. Rival Advanced Micro Devices is widely expected to counter with its "Magny-Cours" Opteron 6100 processors on March 29, to be followed by the long-awaited launch of Intel's "Nehalem-EX" Xeon 7500s on March 30.
The Xeon 5600s are the kickers to the very successful Xeon 5500s, the first server chips Intel got onto the field with the much-needed QuickPath Interconnect. QPI is important because it got processor cores and memory bandwidth back into whack after being out of kilter for years with the old Xeon frontside bus architecture.
With the Xeon 5600s, Intel is increasing the core count from four to six with the top-end parts, but the memory slots per socket remain the same. With 4GB DDR3 DIMMs being affordable and 8GB DIMMs being merely expensive instead of outrageous - as they were a year ago - Intel is counting on DDR3 DIMM capacities to make up for holding the memory slots constant. Moreover, it's also counting on server OEMs being thrilled that they merely have to drop the Xeon 5600s into the same machines they created to support the Xeon 5500s, since they are socket-compatible.
Intel stole a whole bunch of its own thunder for the Xeon 5600 launch back in early February, when it talked about the power gating and security features of the chip at the International Solid State Circuits Conference in San Francisco. The "transformational" Xeon 5500s launched with much anticipation in March 2009 and provided a much-needed goose to the server racket that had been hammered into the ground by the economic meltdown. Intel and its partners are hoping that the Westmere-EP follow-ons can keep building momentum for x64 server sales.
The Xeon 5500s had two or four cores, 4MB or 8MB of L3 cache, and their 730 million transistors were implemented in 45 nanometer high-k process. Having perfected its 32 nanometer high-k metal gate processes late last year with desktop and laptop processors that were announced in January, Intel is deploying the next rev of its 32 nanometer processes to make the Xeon 5600s. That 45-to-32 nanometer process shrink, combined with better power gating to core and now non-core parts of the chip (allowing for the quiescing of segments of the chip that are not in use), means Intel can boost the maximum core count to six and pump the maximum L3 cache size up to 12MB and still stay in the same thermal envelope.
The 32 nanometer, six-core Westmere-EP chip
The Xeon 5600 weighs in at 1.17 billion transistors and is 240 square millimeters in size. It is implemented in two halves of three cores each, as you can see. The core regions have their own clock speed and power supply, and with the tweaks to the Westmere design the L3 cache and memory controller regions - what Intel calls the "uncore" areas - get their own separate power gating. This allows Intel to be a whole lot more stingy about power usage with the Xeon 5600s.
As El Reg previously reported, the Xeon 5600s have had their on-chip DDR3 main memory controllers tweaked so they can support low-voltage DDR3 main memory. This low-voltage memory runs at 1.35 volts instead of the 1.5 volts of standard DDR3 chips, and the net effect is that memory DIMMs run about 20 per cent cooler when using the low-voltage parts without sacrificing performance, Intel said back at ISSCC, but now the company is only claiming a 10 per cent savings in power.
The Xeon 5600 processors, Intel divulged back in February, have a set of native cryptographic instructions that implement the Advanced Encryption Standard (AES) algorithm for encrypting and decrypting data. But in a conference call with journalists, Boyd Davis, general manager of marketing for Intel's Data Center Group, said that the company has also grabbed its Trusted Execution Technology (TXT) security features from the vPro business PC platform and hardened it so it can be used to secure virtualized server environments. Specifically, the TXT functions built into the Xeon 5600 platform can be used to prevent the insertion of malicious software prior to the launching of the hypervisor when a machine boots.
Here's how the Xeon 5600s stack up, and how they compare to the Xeon 5500s and 3400s that have not been replaced in the lineup:
The current Intel one-socket and two-socket server and workstation chip lineup
As with the Xeon 5500s, not every feature is enabled in every chip. In the table above, TDP is Intel's thermal design point rating, in watts. TB is short for Turbo Boost, which is a feature of Xeon and Core chips that allows some cores to run faster when other cores are turned off. HT is short for HyperThreading, which is Intel's implementation of simultaneous hyperthreading and which makes a single core look like two cores as far as the operating system is concerned. AES is short for the AES encryption instructions, and TXT is short for the Trusted Execution Technology, both of which are new with the Xeon 5600s. The number of cores and threads activated in the chip are also shown, as is the unit price for each chip when the chips are bought in 1,000-unit trays from Intel.