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A day may come when flash memory is USELESS. But today is not that day

However sometime in the 2020s it will be. What then?

The era of flash memory is anticipated to run out of road in the 2020s and newer technologies involving resistance and electron spin are poised to take over, delivering higher capacities, greater speed and DRAM-style addressability.

Some people ask if one of these new technologies could actually unify dynamic memory (RAM) and non-volatile memories in a single universal memory tech.

That seems far-fetched at the moment; just finding a working successor to NAND looks like achievement enough.

Of the IT systems companies only IBM and HP are involved in fundamental research areas that have produced breakthroughs in the post-NAND area. The flash foundry operators, such as Samsung, Toshiba and Micron, are more interested in extending the life of NAND and their investment in NAND product processes than in replacing it with something else.

They can’t ignore it, however. Micron has developed Phase-change memory (PCM) and has been manufacturing product until recently. Toshiba has looked into STT-RAM and Samsung has dabbled with STT-RAM as well.

NAND flash memory is odd technology. It is non-volatile, of course, like tape and disk, but it is not byte-addressable. Unlike disk or tape it has to be written in blocks of bytes at a time, with each byte going into a cell.

It also has to have blocks emptied or deleted before fresh data is written to them, meaning that a write cycle involves two processes. Reads are single processes.

As NAND semi-conductor technology reaches the end of its process shrink road, with cells becoming progressively more error-prone and short-lived below 10nm in size, alternative post-NAND technologies are being examined to see if they can deliver the increased density (capacity) that is needed without carrying NAND’s disadvantages.

Users will always want more capacity and more speed, and post-NAND technologies will be needed. Two or three years ago it was thought that the post-NAND future was going to arrive quickly but TLC (three-layer cell) and 3D NAND technology is pushing back the end of the NAND era to the 2020s.

Research engineers are focusing on technologies that are byte-addressable and non-volatile, and also faster to access than NAND, bringing them closer to DRAM in addressability and speed.

Instead of memory being volatile and therefore data needing a separate persistent storage infrastructure (flash, disk and tape), memory will be non-volatile. This will entail deep system software changes so that systems can fully use this “storage memory”.

There are three main post-NAND development thrusts: phase-change memory (PCM), resistive RAM (RRAM) and spin transfer torque RAM (STT-RAM).

Phase-change memory

PCM involves using electricity to change the state of a chalcogenide glass material from poly-crystalline to amorphous, altering its resistance.

Electrical current applied to the material heats it. If it is cooled quickly then the chalcogenide becomes poly-crystalline in structure. A slower rate of heat loss means it has an amorphous structure with higher electrical resistance level

Both Micron and IBM are involved in PCM research, with IBM building a hybrid PCM/NAND card. HGST has also demonstrated a PCM storage product delivering three million IOPS and a 1.5 microsec read latency.


Micron PCM diagram

PCM manufacturer Micron says PCM is one of several emerging memory technologies it is investing in. In 2012 it was shipping PCM product to Nokia for use in Asha smartphones. The chips stored 1Gb, were built with a 45nm process and had an endurance greater than 100,000 write cycles.

A lot has changed since then, however, particularly in NAND prospects with TLC and 3D concepts. Consequently Micron has withdrawn its PCM product from the market as it develops a new process with a lower cost per bit, reduced power need and higher performance.


HP unveiled the Memristor in 2008, positioning it as a fourth basic electrical circuit alongside the capacitor, the resistor and the inductor.

Memristor cells are built from two layers of a semiconductor, titanium dioxide. One layer includes tiny "oxygen vacancies" and the second does not. The layer with the vacancies is conductive; the other is not and its resistance is far, far higher.

By sending a voltage across the device, the vacancies can be moved from one layer to the other, where they stay and alter the cell’s resistance, giving us binary switchability.

This technology, difficult to productise and viewed in some quarters as always just two years from production, is one of the pillars of HP’s ”Machine” development, along with silicon photonics, a new operating system and specialised chips.

Several things combine to reduce the specific impact on the memory area that Memristor technology looks likely to have.

Firstly, HP is treating its Memristor as a proprietary technology to be used in its own proprietary hardware. Also, none of the main flash foundry operators are involved in Memristor development, as far as we know. Hynix, a second tier foundry operator, has been involved.

Thirdly, Memristor is now generally viewed as a Resistive RAM (RRAM) variant and not as a distinctly different non-volatile memory variant.

Resistive RAM

Like PCM, RRAM uses different resistance levels to signal a binary 1 or 0 but without material state phase changing. RRAM generally is built with thin-oxide films and uses applied voltages to alter resistance levels from high to low and back again.

IBM and Crocus Technology have worked on their magneto-resistive RAM concept. Unity Semiconductor had its CMOx technology. Crossbar is another company involved in product development.


Crossbar RRAM

It has 3D RRAM technology and thinks it can build a 1TB – yes, B for byte – chip. Its first standalone RRAM chip will reach 1Tb per die, though. This should have a 100,000 write cycle capability.

We are told it will be byte-addressable for the embedded market but page-addressable, with 1KB pages, for the storage market. Crossbar tells us its process can scale below the 16nm area which is coming to be seen as NAND’s bottom line.

The technology is based on an amorphous silicon switching layer, using ionic metal motion.

Crossbar’s architecture is described as 1TnR, meaning a single transistor drives “n” resistive memory cells. Crossbar says this enables very high-capacity solid-state storage.

In comparison PCM has a1T1R architecture with one transistor driving a single cell, meaning lower-density dies according to Crossbar.

Memristors use the oxygen vacancy phenomenon and this typically requires noble metal electrodes, such as platinum. The company says these are hard to integrate into a fabrication process and asserts metal ions are more reliably controlled than oxygen vacancies.

It adds that Memristor technology typically has to have a complex non-stoichiometric oxide for oxygen vacancy-based switching and is difficult to replicate. Its own amorphous silicon doesn’t require tight stoichiometric control and is easy to replicate.

Crossbar would also partner with a foundry operator to mass produce its RRAM chips, meaning none of the major memory or flash foundry operators have yet decided to go with RRAM technology.

Spin-transfer torque RAM (STT-RAM)

This is the third generally recognised post-NAND technology. Samsung and Toshiba have been active in this area.

Normally an electric current is not spin-polarised, as half its electrons are classed as spin-up and half as spin-down. This can be changed by passing a current through a thick magnetic layer so that it has more spin-up electrons than spin-down or vice-versa.

Next the spin-polarised current transfers its spin direction to a magnetic element from which the direction of magnetism signifies a binary one or zero.

Spin Transfer Technologies, a startup working in the field, calls its technology MRAM. It raised $70m in October 2014 to fund continuing development, which started with a $36m funding round in February 2012. Total funding is thus $106m – serious money for just two rounds.

Samsung also had an involvement in STT-RAM in 2011 when it bought a technology developer called Grandis.

What's the score?

At the moment it is apparent that no major flash foundry has yet put its weight behind a single post-NAND technology. That, in El Reg’s opinion, is because of two things.

Firstly, no clear front-running technology has emerged, with PCM, RRAM and STT-RAM enjoying roughly equal status. While startups such as Crossbar and Spin-Transfer Technologies are pouring their energies into their own developments, the flash foundry operators see post-NAND technologies as something to be left on the back burner.

They are concentrating on pushing NAND density higher through the 3D and TLC initiatives, while lowering latency by moving to NVMe, and possibly flashDIMM interfaces. They see no pressing need to develop anything else until closer to the 2020s.

A respected consultant in this area, Jim Handy of Objective Analysis, says: "I see 2023 as the year that RRAM or some competing technology will displace flash or DRAM. Entrenched technologies will be with us for some time.

"Until then, all the other technologies vying to replace DRAM and flash will be relegated to niches.”

Niches but no riches for post-NAND tech startups, then, at least for the next eight years or so.

Until then flash chips will be be pushed upwards, adding layers and layers of cells to increase capacity, with TLC providing an extra capacity fillip where needed.

There is no general need yet for any system software to take on board post-NAND memory concepts. Developers can breathe sighs of relief for the time being. ®

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