Micron fires off some in-memory flash data rockets

New unit will go beyond selling chips and standard components

Comment Micron’s Storage Business Unit (SBU) wants to shake up the server status quo with a dynamic upstart duo: in-memory app accelerating data processing rockets and instant access, cold data flash vaults.

How it’s going to do that begins with its NAND chip development plans, which we learned about at a Silicon Valley briefing. It starts at the chip level.

Chip tech

Micron currently makes NAND chips in its foundry and builds them into SSDs and PCIe flash cards for use by OEMs and consumers. As an example, IBM uses Micron MLC flash in its FlashSystem all-flash array.

These two basic NAND technologies are developing. Chips are moving from planar 16nm MLC flash to 3D TLC flash using a 4X-3X process in order to achieve better access speed and endurance from the TLC cells. Capacity-wise Micron mentioned that 50TB SSDs were feasible in the future.

Micron is not saying what the process size is; we think it is between 49nm and 30nm. Such chips will enable high-capacity components for in-memory applications using storage memory; SAP HANA type software for more everyday apps.

These TLC 3D chips will evolve into 3D QLC chips, enabling active archive applications, and then there will be a post-NAND future as and when 3D process shrinks run out of steam. Perhaps there will be 3D HLC (6-bits per cell) technology as well.

Moving up the stack to the component level, Micron makes SSDs and PCIe flash cards. These are evolving to use the standard NVMe interface which should enable, as well as faster-than SATA/SAS direct access interfaces, external PCIe fabrics capable of replacing slower LAN links.

Storage BU

The newly-formed Storage Business Unit (SBU) led by Darren Thomas, has been set up to go beyond selling chips and standard (commodity) SSD/PCIe components.

Darren Thomas in Top Gun jacket

Darren Thomas, Micron Storage BU head. Had a beard at Dell, but clean-shaven now

We were told there were four markets for the SBU:

  • After-market upgrades
  • Corporate computing via OEM
  • Enterprise
  • Data Centres for hyperscale and cloud providers; the cutting edge and Google/Facebook style

The first thing the SBU is doing is having collaborative deals with customers. The Micron FortisFlash comes in a non-standard form factor and has been customised at a deep interface level by IBM.

A multi-faceted deal exists between Seagate and Micron, with Seagate now having no strategic relationship for flash with Samsung. Seagate hybrid disk drives, SSHDs, have small amounts of Micron flash added to the disk drive to enable much faster-than-disk access to high priority data.

Micron buys firmware for its SAS SSDs from Seagate, and Seagate uses Micron flash in its Xyratex arrays. There is a rolling five-year deal between Seagate and Micron, which includes a volume Micron NAND chip supply component.

Stack systems

Micron wants to go beyond this level, with Thomas saying that "we're taking a very hard look at taking Micron into the systems level. Watch this space". So what does this mean?

We can envisage Micron inhabiting a value stack landscape running from left (chips) to right (application software) through components, modules, hardware systems, base and system software;


In the chart the boxes in the Chips column represent Micron’s current and forthcoming NAND chip types, flagged as “Future.” Ditto in the Components column with SAS and PCIe interfaces both going to NVMe.

Right of these columns we are in El Reg’s supposition-land. The hardware systems column includes servers, storage arrays, Hyper-Converged Infrastructure Appliances (HCIAs), and embedded systems, like video surveillance kit, PCS, notebooks, tablets and smart phones.

We think Micron’s intention here is to have servers and storage arrays and embedded server systems use large amounts of Micron chips and SSD/PCIe components with storage-class memory combining fast, expensive, volatile DRAM and slower, cheaper and persistent flash.

It wants to have such systems used in two high growth rate areas of the market; latency-critical in-memory applications on the one hand, and latency-insensitive “Big Data and Archive” applications. The diagram shows this, with the central blue area being uninteresting to Micron.

Next page: Possible pathway

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