Western Digital, via its acquired firm SanDisk, along with Toshiba, has started pilot production of 64-layer 3D NAND.
These third generation BiCS3 chips are being fabbed at the Yokkaichi, Japan facilities, operated in a joint venture between WDC and Toshiba.
Currently Samsung is shipping 48-layer 3D V-NAND chips. 64 layers is the next step to increase per-chip capacity further.
Dr Siva Sivaram, EVP for memory technology at Western Digital, has a canned quote: “BiCS3 will feature the use of 3-bits-per-cell technology along with advances in high aspect ratio semiconductor processing. The first chips will have 256Gbit capacities but this will grow to 500Gbits.
BiCS2 48-layer chips have 256Gbit capacities so there is no advantage until higher-capacity chips are produced. This suggests that the 64-layer chips have had a die shrink compared to the 48-layer BiCS2 chips, and WDC/Toshiba is proving the technology and production process before embarking on making higher capacity chips.
Initial BiCS3 product output will start later this year with meaningful commercial volumes starting in the first half of 2017.
OEM sampling of BiCS3 chips will start this quarter, with volume ship of chips for the retail market in the fourth 2016 quarter. Shipments of the current, second generation, BiCS2 3D NAND chips continue to retail and OEM customers.
We can surely expect Samsung 64-layer V-NAND chips to be available in 2017 as well. Intel and Micron are also on a 3D journey, both with NAND and, more excitingly, faster XPoint. Next year is going to be a non-volatile memory high-point. ®
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