WD gets court order: Toshiba can't block access to shared database
Of double negatives, TSVs, TROs, BiCS and JVs
Western Digital Corp has won a temporary restraining order (TRO) preventing its flash joint-venture partner Toshiba from impeding the shipment of engineering wafers and samples to WD in Milpitas, CA, as well as preventing it from blocking certain Western Dig employees from accessing shared databases.
The two parties are in an acrimonious dispute over Toshiba trying to sell its joint-venture interests (a) without WD’s consent and (b) not to WD itself. (Convoluted background here.)
WD is trying to force Toshiba to let Western Digital buy its interest in the pair's joint venture by using a lengthy arbitration court process, lasting beyond a date when Toshiba needs to renew its Tokyo stock exchange listing and for which renewal it is not capitalised enough to make.
It has also filed an injunctive relief claim to try to halt the sale.
Toshiba says this is unfair interference in its memory business auction from which the money will come to save its stock exchange listing and continued operation, and has sued WD for $1bn, and had been denying it access to the Japanese JC facility and databases.
So WDC went to court to win a TRO stopping Toshiba from doing this and has won its case. On Friday a California court will consider the injunctive relief case arguments.
Toshiba and TSVs
Meanwhile flash technology moves on and Toshiba us telling the world it has built a 48-layer TLC (3bits/cell) 3D NAND chip using Through-Silicon Vias (TSVs). This technology, Toshiba says, uses vertical electrodes and via that pass through the multi-layer die to provide inter-layer connectivity at higher speed and lower power than alternative approaches such as wire-bonding.
Toshiba TSV schematic
The power efficiency of a single package is almost twice that of a similar die using wire-bonding. Tosh says TSV BiCS technology enables a 1TB device (SSD) with a 16-die stacked architecture in a single package.
Tosh and WD are developing 64-layer BiCS 3D NAND chips and the prospect is hat TSV technology will be used with it too, should the fabs be able to create the carefully crafted and precisely oriented vias (think integrated internal wires) through 64-layers of flash.
A prototype BiCS technology chip with TSVs will be shown at the 2017 Flash Memory Summit in Santa Clara, California, United States, from August 7-10. Sample product is due in the second half of this year. ®