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Quad goals: Western Digital clambers aboard the 4bits/cell wagon

The bit number explosion gets bigger still

In the flash numbers game Western Digital's 3D, 64-layer NAND is being armed with 4bits/cell (quad-level cell, QLC) and bit-cost scaling (BiCS3) technology.

WD's announcement follows joint-venture partner and legal war opponent Toshiba's QLC reveal in June.

QLC flash chips have a third more cells and double the data density of TLC (triple-level cell) flash.

Once upon a time flash chips came with just one layer of 1bit cells. With today's 64-layer, 3bits/cell chips there has been an explosive increase in the number of bits on a chip and this is set to continue.

Its QLC chip has a 768Gb capacity. Dr Siva Sivaram, executive vice president of memory technology for SanDisk, bigged up WD's QLC implementation. "The most striking aspect in today's announcement is the use of innovative techniques in the X4 architecture that allows our BiCS3 X4 to deliver performance attributes comparable to those in BiCS3 X3," he said.

In other words, its QLC flash performs pretty much at the same level as its 3bits/cell TLC flash. However, it's generally recognised that QLC's endurance will be significantly shorter than that of TLC flash, rendering it suitable for fast-access archival data applications and other read-often, write-rarely use cases.

But its high capacity means that over-provisioning in QLC drives can be used to extend the effective life.

WD will have QLC SSD and removable drives on show at the Flash Memory Summit in Santa Clara next month. Martin Fink, WD executive vice president and CTO has a speaking slot at the event.

WD expects that its in-development 96-layer 3D NAND will come in QLC form as well. ®

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