Backgrounder The flash foundry folk took on 3D NAND because it provided an escape hatch from the NAND scaling trap of ever-decreasing cell sizes eventually to non-functioning flash.
But 3D NAND, the layering of many 2D planar NAND chip structures, will run into its own problems.
These are to do with wafer production time and yield, and layer-crossing component positioning.
With planar NAND we understand the foundry operator runs through a series of deposition and etch processes to lay out the chip’s cell components on the wafer. This takes a period of time and the yield of good cells on the wafer depends upon the efficacy of the process steps.
Now let’s envisage a 2-layer cell structure process. It requires the cell-level components to be laid down a second time, on top of the first layer with appropriate insulating material between the two layers. This will prolong the process time, and also increase the likely number of dud cells, because there are more cell component elements that could have faults in them.
Other things being equal, a 4-layer structure will double up the cell-level process time and faulty cell count compared to a 2-layer structure. A 32-layer structure will add a 16X multiplier to both items, extending wafer processing time and testing time to identify the increased number of dud cells. A 48-layer structure even more.
The flash foundry industry is currently transitioning to 64-layer cell structures - 72 layers in SK Hynix’s case - so the wafer processing and testing time will increase yet again. And it is prototyping 96-layer cells, which will extend processing and testing times yet again.
3D wafers could spend many, many days in a foundry, making the factory less productive on a wafers per month output measure.
Vertical layer-crossing components
A multi-layered chip has components running through the layers, such as Toshiba and Western Digital’s Through Silicon Vias (TSVs). These are holes through the layers and these are not drilled but etched, with plasma beams for example. The etching beam has to be positioned and powered precisely and excessively slight positioning errors at the top of a 96-layer hole could be impressively large ones at the bottom.
Etching TSVs in a 128-layer chip might prove impossible.
One way out is to maintain the layer count but shrink the cell size. Planar NAND was forced to give way to 3D NAND when cell lithography reached the 15-16nm area as NAND cells smaller than that weren’t reliable data stores; there were too few electrons to provide a stable and recognisable charge level.
The first 3D NAND products reverted to larger cell sizes, in the 40nm area. So it would be feasible, possibly, to shrink 3D NAND cells down to the 30nm area and then perhaps the 20nm level. It would make the processing steps more difficult because greater precision would be needed.
The industry can't go lower than 16-15nm because it would encounter the same problems that killed further 2D NAND lithography shrinks.
One way out of the layer trap is string-stacking - the simple layering of already layered 3D NAND chips one above another.
TSV would be constructed through the two layers of layers, so to speak, and so a double string-stacked 64-layer 3D NAND structure would have 128-layers, 2 x 64-layers. Constructing the TSVs would be difficult but it may be that this is the only way to progress beyond 96-layer 3D NAND, or the next iteration of, say, 128 layers.
Possibly we might see 3x or 4x string-stacked NAND chips. The Flash Memory Summit is going to be an interesting event this year and the next as these problems become more visible. ®