Somewhat later than expected, the Peripheral Component Interconnect Special Interest Group, or PCI-SIG, has finally gotten around to releasing the PCIe 4.0 specification, which describes the technical requirements for connecting devices through the PCI Express I/O bus in personal computers and servers.
"The delivery of the PCIe 4.0 specification to the industry is an important addition to our spec library as it delivers high performance 16GT/s data rates with flexible lane width configurations, while continuing to meet the industry’s requirements for low power," said Al Yanes, chairman and president of the industry consortium, in a blog post.
Version 4.0, first announced in 2011, doubles the data transfer rate available in PCIe 3.0, which debuted in 2010. It includes improvements like lane margining (which allows product engineers to assess the electrical margin available in a given system), lower latency, RAS features (reliability, availability, serviceability), and more robust I/O virtualization and platform integration.
The seven year gap between PCIe 4.0 and PCI 3.0 appears to have emboldened other data shuttling schemes. CCIX, which stands for the Cache Coherent Interconnect for Accelerators, counts companies like AMD, ARM, Broadcom, IBM, Micron, Qualcomm, Red Hat, Texas Instruments, and Xilinx as members.
The server-focused consortium in August announced that it had managed to transfer data at a rate of 25 Gbps, three times faster than PCIe 3.0, the current standard, and faster than PCIe 4.0.
That rate is similar to what another interconnection group, OpenCAPI, claims it can achieve.
PCI-SIG may be able to avoid being outpaced by its members through the acceleration of its delivery timeline. PCIe 5.0, announced in June and capable of 32GT/s, is scheduled to arrive in less than two years, Q2 2019.
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Doubling the PCI Express data transfer rate yet again has potential benefits for a variety of modern workloads like machine learning, gaming, and image processing, where large amounts of data get transferred over I/O channels.
"PCI-SIG has been able to accelerate the 5.0 timeline as we have improved the specification development process to minimize review cycles and thereby reduce delays," explained Yanes in an email to The Register. "We focus on delivering specs in a timeframe that our members require."
One change to the process, Yanes said, involves simplifying and streamlining the review of earlier versions of a specification.
"In addition, we were able to accelerate the timeline as the framework for the PCIe 5.0 specification was already in place thanks to improved silicon design processes, key functional enhancements and a future-proofed architectural design set forth in the PCIe 4.0 specification," he said.
Yanes cites several challenges moving from 3.0 to 4.0, including protocol improvements, lane margining, and 16GT/s support.
In version 5.0, Yanes said, the changes will be mainly limited to a speed upgrade. "The PCIe protocol already supports higher speeds via extended tags and credits, and existing PHYs in the industry already run at 28GHz/56GHz. For PCIe 5.0, we will leverage existing techniques out in the industry, new materials like Megtron 6, and new connectors will need to be considered," he said.
IBM's POWER9 processor, expected to ship this year, is said to be the first processor that will incorporate PCIe 4.0. Intel last month showed off its forthcoming 10nm Falcon Mesa FPGA, which includes a PCIe 4.0 interface.
More kit should follow, but with 5.0 so near, don't expect a long-term relationship. ®