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WD to move all its stuff to RISC-V processors, build some kind of super data-wrangling stack

Details are thin, but it looks like disks could help crunch data out on the edge

Analysis Western Digital has grandly announced its will use the open RISC-V processor architecture in all future products and "intends to lead the industry transition toward open, purpose-built compute architectures to meet the increasingly diverse application needs of a data-centric world."

Western Digital, aka WDC, CTO Martin Fink outlined the vision this week, at the 7th RISC-V Workshop held at WDC's Milpitas offices.

Exactly what he meant isn't clear.

It is highly likely WDC uses Arm-compatible processors – such as Arm9 and Cortex-M3 parts – for the in-drive controllers in its disk and flash drives, and also uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.

Hardly anybody cares about what embedded processors WDC, or any other hard disk vendor, uses in its drives. They just do their job silently and hardly anybody cares about the architecture they employ.

Fink's explanation for why we need to care is that WDC is transitioning from a data storage company to a data technology company. That may mean it needs a little more processing power, but Arm and its chip-making partners have a fat range of designs to choose from if you want to a beefier microcontroller.

The move from Arm to RISC-V could be because WDC wants greater or full control over its CPU cores, and without having to toss some coins to Arm and Intel. Even if it does go down the RISC-V route, WDC will need to pay someone to design and make the system-on-chip controllers anyway, so it's not clear whether any cost savings in using RISC-V will be significant; perhaps they will be. It really depends on how much of a tax Arm charges to use its blueprints and patents.

The RISC-V instruction set is very similar to Armv8 and, to us, looks like MIPS Part Two. Founded at University of California, Berkeley, by Krste Asanović, RISC-V was worked on by Professor David Patterson, who back in the day led the Berkeley RISC project – a CPU design research effort that gave birth to SPARC. Today, textbooks on RISC-V are authored by Patterson and Professor John Hennessy, who founded the MIPS architecture. The Berkeley RISC project and the MIPS design team were loosely linked in the early 1980s.

Thus, RISC-V is, in a way, a reunion of the original early SPARC and MIPS brains, and has everything going for it despite being about seven years old. It is a BSD-licensed 32, 64 and 128-bit CPU architecture that right now is being implemented in small, low-power but fast embedded chips, and can scale up. It's also used as a case study to computer engineering undergraduates.

Mike Cordano, WDC president and COO, declared: "Western Digital is a leader in storage products and technologies, and we are now expanding that leadership to open, data-centric compute architectures ... We are moving beyond just storing data to now creating entire environments that will enable users to realise the value and possibilities of their data.”


Emergence of Big and Fast Data

Behind those words is the company's belief that there are now two types of data that matter: Big Data and Fast Data.

Fink's slides [PDF] and a presentation brief [PDF] offer a familiar explanation for Big Data as old records that are analysed long after their creation.

Fast Data by contrast, needs to be analysed for real-time responses.

Fink opined that the processor, memory, I/O and storage needs of processing systems for these two data types are diverging fast and converging away from the way data is managed and processed today.

One size does not fit all

WDC's response is independent component-level scaling of processor, memory, IO, and storage. The company also wants "An open architecture to avoid dependency on a particular vendor or technology."

There's not much in Fink's presentation or accompanying documents that explains what WDC will actually build or sell to turn these words into products.

There's a hint in the presentation brief's idea that "At the micro-level of integration, application and specialized data can be added to storage devices, such as hard disk drives (HDDs) or solid state drives (SSDs), as well as storage platforms that integrate these devices into larger storage pools."

That sounds like disk drives with enough CPU power to participate in analytics, or let themselves be assembled into virtual pools, or both.

The brief also outline a macro-level implementation that could see "the embedding of data analytics or machine learning resources, and into high-scale data storage systems." That sounds like arrays-as-analytics-boxen. WDC advanced its own ActiveScale object-based storage (OBS) system as suitable for this role.

WDC also talks about supporting data-centric computing architectures at the [Internet of Things] edge, where it has no specific products or technologies. Fink said the company "wants to bring compute closer to data". That could again be individual disks smart enough to do some analytic. And with storage appearing in almost every device, that's an interesting prospect.


Why did WDC reveal this all at a RISC-V conference and tell the world it'll start pumping out billions of RISC cores each year? Especially given most people just want stuff to work and don't care about silicon architectures?

Because WDC recently made a strategic investment in Esperanto Technologies, a developer of high-performance, energy-efficient computing solutions based on the open RISC-V architecture. That's why. Oh and Esperanto has a machine learning focus.

El Reg comment

WDC can use whatever processors it likes in its devices. But as soon as it starts using RISC-V processors, and software, in environments where its systems have to interact - and given x86 is ubiquitous in the data centre, so is the need for interaction - it big challenges to get everything talking and will be susceptible to FUD-flingers.

There are reasons x86 and Arm are dominant, not least colossal ecosystems of code backing both. WDC is being very bold indeed if it thinks choice of processor architecture alone will help it win.

In WDC's favour is that the IoT is in its early days. The most-discussed way of capturing and analysing data is to connect things to an x86 server, which does local pre-processing and some real-time analysis but hands off the hard work to a data centre. WDC's Fast Data idea may mean that arrangement is too slow.

A stack in which a common architecture lives on lots of layers might be better. But until its RISC-infused products are detailed, and emerge from 2019 onwards, it's unclear exactly what the company is up to and how it plans to pull it off.

We've asked WDC for more details. If it delivers, we'll let you know. ®

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