China’s state-backed 3D NAND fabber, YMTC, has claimed it will bring out memory speed flash chips next year.
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Yangtze Memory Technologies Co (YMTC) is developing a 64-layer 3D NAND with a potential 3Gbit/s data access speed, supposedly equivalent to DDR4 memory.
YMTC said its 64-layer 3D NAND chips would enter mass production in 2019, with the plant churning out up to 300,000 wafers/month, for use in smartphone, personal computing, data centre and enterprise applications. We cannot confirm the chip's speed will actually approach that of DDR4 memory.
Simon Yang, YMTC’s CEO, emitted a canned boast:
At present, the world’s highest 3D NAND I/O speed is targeting 1.4Gbit/s while the majority of the industry is offering NAND I/O at 1.0Gbit/s or below. With our Xtacking technology, it is possible for NAND I/O speed to reach up to 3.0Gbit/s, similar to [the] I/O speed of DRAM DDR4. This is going to be a game changer in the NAND industry.
YMTC’s 32-layer chip will have two-thirds of the 96 layers seen in devices beginning to enter production in the Intel/Micron, WD/TMC and Samsung foundries. But this disadvantage could be more than negated if - and it's a big if - the chip is actually three times faster.
In fact, if it were that speedy, it would be a faster non-volatile memory than Intel’s 3D XPoint.
The Xtacking tech is similar to Micron's CMOS-under-Array (CuA) set-up, which has the chip’s peripheral logic circuitry built underneath the NAND layers, thus decreasing the overall chip area. YMTC is putting its logic circuitry on top of its chip instead of underneath.
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Yangtze Memory Tech, state-backed and majority-owned by Tsinghua Unigroup – pointed out that in conventional 3D NAND designs (but presumably not those of Micron), the periphery circuits take up to 20-30 per cent of the die area, lowering NAND bit density. As 3D NAND technology continues to progress to 128 layers and above, the periphery circuits will likely take up more than 50 per cent of the total die area.
The Chinese domestic chip-fabber's Xtacking technology ostensibly sidesteps that problem and also – though it is not explicitly explained how – opens the door to speed increases.
YMTC has a China-chest-thumping video on its website, which provides scant detail.
The chip is built starting from separate NAND and peripheral circuit wafers. The peripheral circuits look after data IO and memory cell operations. These are designed to achieve a desired function set and IO speed. There is no hint as to how a 3Gbit/s speed could be achieved.
The statement from YMTC claimed: “Once the processing of the array wafer is completed, the two wafers are connected electrically through millions of metal VIAs (Vertical Interconnect Accesses) that are formed simultaneously across the whole wafer in one process step.”
The claim is that this design enables much higher NAND bit density than conventional 3D NAND. Also there can be independent development and processing of the array and periphery circuits – thus enabling “a modularised, parallel approach to product development and manufacturing, reducing product development time by at least three months and shortening manufacturing cycle time by 20 per cent, significantly accelerating 3D NAND time-to-market.”
The manufacturer also suggested that customised NAND products could be built with unique and specific functions in the peripheral logic circuitry. That could appeal to OEM customers.
Analyst Jim Handy from Objective Analysis said: "Toshiba and PMC Sierra pioneered the use of a separate logic chip for stacked NAND speeds two to three years ago, showing a stacked NAND at the Flash Memory Summit.
"This is a slightly less expensive rendition since it doesn’t use [Through Silicon Vias] but employs face-to-face bonding which limits it to a single NAND chip per logic chip. It does give you speed, but NAND flash is a pretty slow medium. The market will decide whether this is worth it." ®