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Linux lobby org joins with RISC-V bods to promote open chip spec

Two foundations find common cause promoting in populist processor plan

The Linux Foundation, the non-profit funded by for-profit tech firms to promote the open source operating system, has begun working with the RISC-V Foundation, another non-profit backed by well-heeled companies, to encourage adoption of the open RISC-V instruction set architecture (ISA).

The two organizations on Tuesday plan to announce a collaboration to enhance the appeal of the RISC-V ISA, tech that proprietary chip designer Arm recently tried to stifle. The results of the tie-up should come in the form of training programs, tool development, community building and governance, marketing support, and legal advice.

In a phone interview with The Register, Rick O’Connor, executive director of the RISC-V Foundation, said the collaboration is really about bringing together the Linux and RISC-V communities to enhance adoption.

"The ISA is arguably the most important interface in a computer system," said O'Connor. "It's where software meets hardware. There's a lot of overlap in our respective ecosystems that will create a fair amount of synergy."

RISC-V began taking shape in 2010. The project, backed by boffins at the University of California, aims to create a viable free and open processor specification as an alternative to proprietary designs. While the spec is open, the final implementation of a RISC-V CPU core may, depending on the designers, be open or closed sourced. There are various open-source RV cores out there to drop into your custom system-on-chip as you wish.

The countercultural instruction set has evolved rapidly and has reached the point where commercial RISC-V hardware has started to appear in the market, such as SiFive's Freedom system-on-chips. A year ago, for example, storage biz Western Digital committed to using RISC-V cores in its future products.

But RISC-V remains a work in progress. For instance, it doesn't have a complete hypervisor specification, a feature that is necessary, for example, for RISC-V server chips.

O'Connor nonetheless maintains that the RISC-V ISA is suitable for all types of requirements, or will be eventually.

"There' a fair amount of enablement work that needs to happen," he said. "There's active development ongoing on all of those fronts."

People involved in the project have been playing around with virtualization and other forms of abstraction, said O'Connor. He doubts virtualization will debut in 2019 but said, "Certainly by 2020," even as he cautioned, "Every prediction we've made, we've underestimated the speed the marketplace is moving."

Room with many locks on door

Arms race: SiFive, Hex Five build code safe houses for RISC-V chips


Interest in RISC-V, said O'Connor, isn't necessarily driven by the free and open nature of the spec.

"If you have a hammer already, and I say, 'I have a hammer and it's free,' it may not be much more useful to you," he explained. "The challenge that we face with computing platforms is a performance challenge."

The problem, O'Connor said, is that Moore's Law is dead or nearly so.

"The semiconductor industry arguably has been lazy," he said. "There hasn't been significant innovation around the systems we build for quite some time. We're pretty much building the same thing we've always built, relying on geometry reduction to get better performance. That gravy train is dead."

What RISC-V enables, through its lack of licensing, is the ability for anyone to experiment with chip designs tuned to specific needs. You can design a custom chip and whack in two, four, eight, or 128 RISC-V cores, if you wish, for example. If you have an idea for an accelerator, and need some CPU power alongside it, now you can concentrate on the hardware acceleration, and drop in your RV cores as needed, and then run Linux or some other operating system as well as familiar applications on the thing.

"It turns out the extensibility and flexibility of the RISC-V ISA is the ideal toolset for purpose-built machines to get the best power and performance tradeoffs," he said. ®

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