If you hate writing Verilog, VHDL, and other hardware design languages, used to craft computer chips and configure FPGAs, you're far from the only one.
This Register vulture wrote Verilog for gate arrays in the early 2000s, and how did that work out? He ran screaming into the, at the time, more exhilarating world of journalism.
Your humble hack wasn't the only one loathing these design languages, it seems: enough application-level software developers have now made their unhappiness with Verilog et al clear to FPGA design house Xilinx that the biz has had a rethink of its tooling.
As such, Xilinx has said it has rejigged its software to allow application programmers to more easily configure its FPGAs using a high-level language, particularly if they want to use Xilinx chips to accelerate machine-learning algorithms.
The goal is to allow engineers way up the stack to customize FPGAs to accelerate their algorithms, be them machine-learning inference or heuristic packet filters, or whatever, in hardware, without having to know how to write painful hardware design code. Application code can then offload parts of their processing to these chips, which perform the algorithms fast in hardware.
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Specifically, Xilinx has produced a toolchain called Vitis, which will be available for free from November 1, we're told, and is set to be an alternative to the heavy-duty Vivado suite.
According to Xilinx, you can use Vitis to compile C/C++ algorithms down to logic, and use that to configure an FPGA, or you can write AI code that is combined with Xilinx's deep-learning acceleration engines and then slotted into an FPGA, or a mix of both approaches.
Either way, application-level code, be it C/C++, or Python, or whatever, calls down to libraries that interface with the algorithms you've implemented in the attached FPGA, configured using Vitis, offloading AI inference and other work to the chip. You can write these intermediate libraries yourself, or use Xilinx's open-source offerings, though if you want to integrate your software with the deep-learning engines, you'll need to use the FPGA slinger's libraries. Vitis can program any Arm-compatible CPU cores in an FPGA, too.
And, yes, you can already do this sort of thing with Xilinx's Vivado suite, compiling C down to logic, and utilizing Xilinx's proprietary AI engines. However, this latest stuff is supposed to be easier to use, and doesn't involve Vivado, which varies in price – from free to not so free – depending on the edition you want. In fact, these new tools are supposed to plug into whatever software development environment or IDE you normally use.
Vitis will be announced today at the Xilinx Developer Forum in San Jose, USA.
Ramine Roane, Xilinx's veep of software and AI product management, told El Reg this is an acknowledgement by the FPGA house that Verilog et al are too much of a pain for software developers who just want to write app-level code and have it accelerated in hardware. These programmers have been demanding something easier to use than Vivado for years, apparently. As such, Vitis has been in development for five years to appease app devs, according to Xilinx.
"It's really hard to do hardware design," Roane said yesterday ahead of today's launch. "Our tools are good, but you need a PhD in hardware design. While those people exist and they do a good job, the wider community is developing software in Python and Tensorflow and Pytorch."
"Vivado is never going away," Roane added, stressing that Xilinx will offer two streams of development tools: Vitis and Vivado.
Xilinx's pitch for Vitis is, basically, if you design a chip specifically for accelerating a particular algorithm or machine-learning model, by the time you come to deploy said ASIC, the technology may be out of date. However, with an FPGA, programmed from a high-level language, you can update your custom hardware acceleration without having to buy or fabricate new parts. Your mileage may vary.
"You can build new acceleration architectures every three months if you need to, without needing new silicon," Roane argued.