A bridge over troubled water: Intel teases Ponte Vecchio, the GPU brains in US govt's 1-exaFLOPS Aurora supercomputer

If at first you don't succeed, Phi Phi again

SC19 Intel today confirmed the identity of the GPU-based math-accelerator chip it will offer to supercomputer builders.

The announcement of the Ponte Vecchio part, named after that medieval bridge in Italy, coincided with the start of the Supercomputing 2019 conference in Colorado, USA, on Sunday.

Ponte Vecchio will be fabricated on Intel's forthcoming 7nm node, and not its troubled 10nm process. It will use Chipzilla's exascale Xe architecture and Foveros and EMIB packaging, and support high-bandwidth cache and memory and CXL-based interconnects.

It is described as a general-purpose GPU albeit one tuned for AI and applications found running on top-end supers – think physics simulations and weather modeling and the like. You won't be able to buy this as a gaming graphics processor. But yes, it could probably, perhaps, possibly run Crysis. It will, according to Intel, offer high throughput of double-precision floating-point calculations, and sport vector matrix math engines.

Not much else is known about Ponte Vecchio publicly. It is likely to arrive in 2021 as it will form the brains of the US government's $500m 1,000-petaFLOPS Aurora supercomputer, which will glue Ponte Vecchio accelerators to Intel Sapphire Rapids Xeon processors, as well as blobs of storage and other bits of technology.

In fact, we're told each Aurora compute node will sport dual 10nm Sapphire Rapids processors and six Ponte Vecchio chips, all using a unified memory architecture between the CPU and GPU cores. The Cray-built monster will span more than 200 racks, and have at least 10PB of RAM and 230PB of storage.

This is, by the way, Intel's second crack at rolling out Aurora: its earlier attempt using its many-core Xeon Phi chips caused it to miss Uncle Sam's deadlines, forcing it back to the drawing board to come up with another approach. Now Chipzilla's returned with its Ponte Vecchio GPUs to hopefully accelerate Uncle Sam's number-crunching to exascale levels.

If you're keen to get your hands on this sort of tech, don't forget Intel previously promised to ship 7nm data-center-grade GPUs in 2021.

Intel will also this week talk up its oneAPI programming interface for controlling systems that use a mix of CPU and GPU cores, FPGAs, and other silicon. This API will also be used in Aurora. Think of it as Intel's answer to Nvidia's CUDA.

Speaking of Nvidia, Intel will use a CXL-based interconnect called Xe Link to connect the Ponte Vecchio accelerators, kinda like Nvidia's NVSwitch, in Aurora and other systems. Competition in this space is heating up.

Finally, you can request remote access to Intel hardware to test and evaluate projects, including oneAPI gear, using Chipzilla's Devcloud.

You can follow this year's Supercomputing conference news, and dive deep into big-iron tech, by heading over to our HPC sister site, The Next Platform. ®

Other stories you might like

  • Software Freedom Conservancy sues TV maker Vizio for GPL infringement

    Companies using GPL software should meet their obligations, lawsuit says

    The Software Freedom Conservancy (SFC), a non-profit which supports and defends free software, has taken legal action against Californian TV manufacturer Vizio Inc, claiming "repeated failures to fulfill even the basic requirements of the General Public License (GPL)."

    Member projects of the SFC include the Debian Copyright Aggregation Project, BusyBox, Git, GPL Compliance Project for Linux Developers, Homebrew, Mercurial, OpenWrt, phpMyAdmin, QEMU, Samba, Selenium, Wine, and many more.

    The GPL Compliance Project is described as "comprised of copyright holders in the kernel, Linux, who have contributed to Linux under its license, the GPLv2. These copyright holders have formally asked Conservancy to engage in compliance efforts for their copyrights in the Linux kernel."

    Continue reading
  • DRAM, it stacks up: SK hynix rolls out 819GB/s HBM3 tech

    Kit using the chips to appear next year at the earliest

    Korean DRAM fabber SK hynix has developed an HBM3 DRAM chip operating at 819GB/sec.

    HBM3 (High Bandwidth Memory 3) is a third generation of the HBM architecture which stacks DRAM chips one above another, connects them by vertical current-carrying holes called Through Silicon Vias (TSVs) to a base interposer board, via connecting micro-bumps, upon which is fastened a processor that accesses the data in the DRAM chip faster than it would through the traditional CPU socket interface.

    Seon-yong Cha, SK hynix's senior vice president for DRAM development, said: "Since its launch of the world's first HBM DRAM, SK hynix has succeeded in developing the industry's first HBM3 after leading the HBM2E market. We will continue our efforts to solidify our leadership in the premium memory market."

    Continue reading
  • UK's ARIA innovation body 'hasn't even begun to happen' says former research lead

    DARPA imitator not doing much after two years of Johnson government

    Updated The UK's efforts to copy US government and military innovation outfit DARPA are stalling, according to a leading figure in research and development.

    Appearing before the Science and Technology Committee, Sir John Kingman, former chair of UK Research and Innovation, told MPs this morning that ARIA – the Advanced Research and Invention Agency – was a good example of departmental research spending that could be cut, sidelined or delayed.

    "A very high-profile example would be ARIA, which has been this big plan for the Boris Johnson government, and yet here we are a few years into the Johnson government and it still hasn't even begun to happen," he told MPs.

    Continue reading

Biting the hand that feeds IT © 1998–2021