Updated The RISC-V Summit kicks off in Silicon Valley today, and there were a few interesting announcements this morning.
These software-generated cores, dubbed the SiFive Intelligence series with the first being the VI2, are configurable by system-on-chip designers: you can control the size of the supported vectors by tweaking the VLEN parameter. The default is 512 bits, and can run up to 4,096. Vector math is useful for accelerating machine-learning algorithms, signal processing, and so on – pretty much all modern microprocessors feature this sort of stuff. The Intelligence cores can execute software in- and out-of-order, too.
Here's what SiFive's spokespeople told us last night:
With the RISC-V Vector Specification, the maximum vector length can vary, dependent on the VLEN parameter. In SiFive Intelligence cores, VLEN is a configurable hardware parameter, as is the datapath width that determines the amount of vector computation per cycle that can be performed. SiFive Intelligence is comprised of several VI core generators where the VI2 series is the first we’re publicly talking about.
The initial default configuration of the VI2 series is capable of 128b/cycle processing to offer focused power and area benefits while offering ~9X increase in performance on 32-bit vector floating point operations across a variety of DSP workloads. The default vector length (VLEN) in this initial VI2 series configuration is 512b, which can be extended to 4096b through combining vector registers using LMUL. The datapath width and VLEN on VI2 series will be configurable both down or up for area/power constrained or higher performance deeply embedded compute applications, respectively.
SiFive designs multi-core 32-bit and 64-bit RISC-V system-on-chips and related tech, and makes the blueprints and code available to all under various licenses, from free to not-so-free. These designs are configurable or customizable, so you can tune the internal components to suit your applications.
The startup is, in our eyes, a fixer in the RISC-V world: the instruction set spec is open, there are plenty of open-source implementations of compatible processor cores out there, and you can run these on FPGAs, but to get them into custom shipping silicon, you will probably need someone to hold your hand through to fabrication. And that's what SiFive will do for you, for a price natch.
The biz is on a roll at the moment. Its Learn Inventor Internet-of-Things widget can be linked to Amazon Web Services. It also unveiled its Apex processor design series designed for "mission critical" workloads.
Following on from its RISC-V-compatible open-source SweRV core EH1 released at the turn of the year, Western Digital today teased the RISC-V-compatible SweRV EH2. It is described as the industry’s first multi-threaded, commercial, embedded CPU core, and includes "double fetch buffers, instruction buffers, commit logic and other microarchitecture enhancements."
It is 32-bit with a nine-stage pipeline. You can find more information here.
WD also teased its tiny RISC-V-compatible SweRV Core EL2, which is described as featuring "a 4-stage pipeline and is designed to replace sequential logic and state machines in controller system-on-chips."
Wind River today said VxWorks, a grandee in the world of real-time embedded operating systems, now supports RISC-V-compatible hardware. This is the OS that powers stuff like spacecraft, aircraft, cars, home electronics, and similar gear. ®
Updated to add
Samsung says it plans to use RISC-V cores in the mmWave RF portion of its 5G cellular modems in its flagship phone products, due to land in 2020. And it is using RISC-V in image sensors, and potentially AI processors and security components. We understand that Samsung will be using SiFive-designed CPU cores in its chips.
Microchip is also teasing a PolarFire system-on-chip that includes five 64-bit SiFive CPU cores and an FPGA. Development boards featuring the chip should be available next year.