Column How well does Intel sleep? It's just rounded off a record year with a record quarter, turning silicon into greenbacks more efficiently than ever, redeeming recent wobbles in the data centre market and missteps in fabrication with double-digit growth.
The company should be slumbering with all the unworried ease of Scrooge McDuck on a mattress stuffed with thousand-dollar bills. Yet the wake-up packet of unease should be pinging its management port with some insistence right now.
Intel remains a one-trick pony, entirely dependent on the x86 ISA. It has no game in GPUs, it is tuning out of its 5G interests, it has long handed over handsets to Arm. It has memory, it has Wi-Fi, it has wired networking, but compared to the cash cows of edge and central x86, these are barely cash coypu.
One barbarian is at the gates with a refurbished siege engine. AMD has finally got its architectural, process node and marketing acts together and is making up for lost time while Intel is still recalibrating from 10nm disappointment. Yet this is familiar turf for Intel, which remains a very formidable machine with enormous resources and flexibility. When AMD still had its own chip fabs a decade or so ago and was having its own process woes, it suffered: Intel is making record profits. It knows how to sell chips on its own turf. It'll have some bumps getting out of 10nm and the next couple of years may not be quite such record-breakers, but x86 remains its to lose.
The smaller, nimbler and more exciting competitor is going to be harder to defend against in the long term. As it prepares to celebrate the 10th year since its inception, RISC-V is showing the most dangerous trait in any competitor, the ability to redefine the ecosystem.
RISC-V has its conceptual roots in 1980s Berkeley, in part as a direct reaction to the trend towards increasing CPU complexity exemplified by Intel's development of the 8080 via the 8086 into the 80386 during the same epoch. That added instruction set features in silicon as Moore's Law made more transistors affordable; RISC went the other way, keeping the core features small and using Moore's Law to speed them up.
RISC-V, as a collaborative foundation of semiconductor companies, was formed in 2015.
As an architecture, it came into being in 2010, again at Berkeley, in the Parallel Computing Laboratory funded – oh, the irony – by Microsoft and Intel. It absorbed all the lessons of the previous 30 years, not just architecturally but in how the industry itself worked. The RISC idea saw some success among traditional processor companies, but the big winner was the British upstart Arm – technically clever and with what proved a killer processing power per watt advantage, but which really shone because it was licensed, not made. Manufacturers bought the design, not the chip, and mixed it in with their own circuitry. Couldn't do that with Intel.
RISC-V takes that further. The obvious advantage over Arm is that RISC-V's instruction set architecture is open source; you can just use it as you wish without paying royalties. But like open-source software, the fact its free is misleading. You can buy a feature phone with an Arm-based chip in it for a tenner: whatever pennies of that go in CPU licensing don't matter. What RISC-V has that Arm doesn't is extensibility. If you need to add features in the instruction set, go ahead. If you need to tune for very low power or very high throughput, you can.
Even that wouldn't be much of an advantage by itself. Designing architectural innovations in silicon is like architecture in brick; easy enough on paper, but until you build the bugger you can't be sure it won't fall down. The process of checking a design for reliable operation is called verification, and when you have a billion-transistor-class CPU with near-infinite permutations of state you only get to verify as much as you can afford: nowhere close to the whole thing. ARM, Intel, AMD, IBM et al spend a lot of time and money in verification so they can sell a complete design with a plausible "Trust us" stamp on it. If you're building your own RISC-V design and can't afford equivalent verification, how do you trust yourself?
RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G...READ MORE
The good news for the RISC-V ecosystem is that verification tools are appearing that automate the process as far as possible. Open source means the majority of your CPU design has been very well tested; your innovations live in an understood and exercised environment, just as open-source software has produced an exceptionally stable yet extensible environment. Conversely, the "Trust us" stamp is looking quite tarnished. Heart Bleed, Spectre and the very latest Intel Management Engine vulnerability are all either signs of verification failure or, even worse, problems that came out during verification but were too expensive to fix and too dangerous to admit. That's why buildings fall down.
So, at the same time as the monolithic approach to CPU design is looking the most vulnerable, the RISC-V approach is getting the same momentum as open source software did in the Noughties. It's in supercomputers. It's in IoT. Samsung is making it. The tools are appearing, the people are learning it, it's becoming the right answer to a lot of questions.
To be fair, Intel shouldn't be losing as much sleep over RISC-V as Arm, which now runs the risk of being another of SoftBank's brilliantly timed investments. Yet the openness and expanding ecosystem of RISC-V has the potential as no other competitor does of restricting Intel's home-turf advantage, much as Microsoft lost the web and mobile to open-source software based on common architectural ideas.
It doesn't matter how good a dinosaur you are if your environment changes. That's what RISC-V represents. ®