Intel plans to debut its third-generation "Cooper Lake" Xeon Scalable processors today, alongside revised Optane memory, 3D NAND SSDs, and an FPGA tuned for AI workloads.
"We've got over 35 million Xeon Scalable processors deployed and Xeon is the foundation of the world's data-centric infrastructure," Lisa Spelman, corporate veep and general manager of Intel's Xeon and memory group, told a media briefing on Monday. "The third gen really evolves our four and eight-socket processor offerings."
Intel's third-generation Xeon Scalable processors, now shipping to corporate customers, are designed for data centers and networking environments, particularly those that handle workloads associated with deep learning, virtual machines, in-memory databases, and analytics.
The 14nm "Cooper Lake" Xeons offer up to 28 cores per processor and up to 224 cores per chip in an eight-socket configuration. There's also a four-socket configuration, and Intel plans to deliver 10nm one and two-socket configurations ("Ice Lake") soon, with a next-generation Xeon release called "Sapphire Lake" scheduled for 2021.
The "Cooper Lake" chips support up to six Ultra Path Interconnect (UPI) channels; up to six channels of DDR4-3200 MT/s; 16Gb DIMMs, with up to 256GB DDR4 DIMMs per socket; and Intel Advanced Vector Extensions 512 (AVX-512).
The server chips have gained support for bfloat16, a custom encoding format for representing numbers in 16 bits that's used for machine learning and Vector Neural Network Instructions. Together, these AI-oriented enhancements are referred to as Intel Deep Learning Boost, a feature set introduced in 2019.
In conjunction with Intel-optimized distributions of AI frameworks like TensorFlow and PyTorch, customers can look forward to more efficient number crunching. Intel claims its Deep Learning Boost iteration can deliver 1.93x faster training for image classification and 1.87x faster inference performance for image classification, compared to the previous Xeon generation.
More generally, Intel says third-gen Xeons manage 1.9x performance on "popular workloads" and up to 2.2x more VMs compared to four-socket server chips from five years ago.
Chipzilla is also revealing its Stratix 20 NX FPGAs, the company's first FPGA tuned specifically for AI tasks. The FPGAs implement arrays of lower-precision tensor arithmetic blocks intended to handle calculations involving matrices and vectors. Intel claims its specialized FPGAs deliver 15X more INT8 throughput than its Stratix 10 FPGA, which implements a digital signal processing block rather than a tensor block.
"The introduction of the AI tensor block delivers as much as a 15X for performance gain for AI applications and brings new innovative capability to Intel's broad silicon and software portfolio for AI," said David Moore, corporate VP and general manager of Intel's Programmable Solutions Group.
Stratix 20 NX, due anytime between July and December, also includes 3D stacked HBM2 high-bandwidth DRAM so large AI models can be stored on chip and supports transceiver data rates of up to 57.8Gbps using PAM4 [PDF] encoding.
To complement its four-socket Xeons, Intel is shipping its Optane Persistent Memory 200 series, which, when wedded to compatible Intel processors, offers up to 3TB of PMem per socket and total memory capacity of 4.5TB per socket, including DRAM.
Lastly, Intel is making its 3D NAND SSDs – D7-P5500 and SSD D7-P5600 – available. They include a power loss data protection scheme and various firmware enhancements like dynamic namespace management, additional security features, improved SMART monitoring, Telemetry 2.0, and optimize TRIM architecture. ®