Marvell will today formally open the doors of its bespoke tailor shop, though rather than cutting and sewing cloth, it's crafting custom 5nm semiconductors.
Simply put it'll work like this: imagine you're an organization that wants to design its own computer chip to efficiently process a particular workload, such as machine-learning, 5G networking, or network security, or why not all three?
You approach US chip giant Marvell, and pick and choose blocks of technology from its semiconductor library – such as its Ethernet and Flash memory controllers, network interfaces, and AI and encryption accelerators – that your custom component will need.
You'll probably drop in some Arm CPU cores, too, to run application code, and then you'll probably slot in some of your own circuitry to speed up or process your specific workloads.
You pass the final blueprint to Marvell, and it supplies you the final silicon chips for you to pop into your products, be they boxes you sell to your own customers, or machines you deploy into your own networks if you're a telco, upper-tier cloud provider, or ambitious enterprise.
This ASIC-as-a-service is the formalization of relationships Marvell has had with its customers for a while now. If you're ordering, say, a million parts a year from Marvell, all designed by Marvell, you can probably, as a large customer, ask for a few tweaks here and there to the design to suit your gear. We suspect these customer requests got to the point where Marvell decided to make it a formal process, dubbing it a "comprehensive custom ASIC solution."
Marvell has already offered this solution to a select few customers, despite announcing it officially today, and their custom chips will ship within the next year, a spokesperson told us.
The fine print
That's the high-level view. Let's look a bit closer at the nitty-gritty, which we've gleaned from conversations with Marvell staff. First of all, if you want a custom part, you'll start a dialog with Marvell, and set out what you want from the chip. Marvell will draw up an upfront non-recurring engineering fee for you to pay, and you'll agree on a per-chip price.
While Marvell's laying out the blocks you requested on the die floorplan, your own in-house chip design team produces and hands over the blueprints to the custom circuitry you want in the chip. This could be a math engine to accelerate a lesser-used AI algorithm, or some kind of data processing pipeline.
You also get to choose, we're told, from Marvell's entire library – no sacred cows are held back, though ultimately, you own your intellectual property, your custom bits, and Marvell still owns its intellectual property: the library blocks you selected. Marvell believes it has a broad selection of tech to choose from – everything you'd need to make a data-center-grade system-on-chip, including 112G SerDes.
How much you want to customize the ASIC is up to you; it could be a little, it could be a lot.
A Marvell illustration of the customization levels available: from left, an example of a Marvell non-custom chip that is one of its standard chip products; a tweaked ASIC with customer-specific interfaces and accelerators; and customized ASIC containing customer-provided designs (click to enlarge)
Eventually, about a year to 18 months later, typically, everything will be combined, simulated, verified, and ready for tape-out prior to fabrication. Marvell will then liaise with, say, TSMC to manufacture the chips using a suitable process node, 5nm, say, and then you buy the chips from Marvell at the agreed per-chip price just as if you were buying one of Marvell's non-custom standard products.
Marvell will also sort out the contracts and royalties with Arm, if you use Arm-compatible CPU cores, such as those in the ThunderX3, and don't already have a relationship with the Softbank-owned microprocessor house.
Working with TSMC also means you get access to things like multi-die chip packages, allowing HBM2, transceivers, PHY, interconnections, and other chiplets to be placed within the same package as the main die. It doesn't have to be a one-die-per-package basic ASIC.
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We wondered if there was a minimum order requirement, and a spokesperson told us: "There isn't any explicit criteria for minimum order volume. However, there is a need for Marvell to prioritize our ASIC design projects as a constrained engineering resource, which does mean we are more inclined to close business on higher volume and revenue opportunities."
In other words, you have to make it worth Marvell's while since it'll be doing all the back-end heavy lifting. On the other hand, the final bill can't work out more expensive than just going it alone without Marvell's help.
Kevin O’Buckley, general manager of the ASIC business unit at Marvell, estimated to us that, outside the Marvell program, just getting to the first spin, the A0 stepping, of a straightforward 7nm system-on-chip would typically cost $50m in engineering time, mask fabrication and other manufacturing costs, and other expenses.
Thus, Marvell has to ensure its bespoke tailoring remains price competitive in that context: it can't be more expensive than a customer setting up its own in-house ASIC team and project costing tens, if not hundreds, of millions of dollars.
One way Marvell can keep a customer's final custom ASIC bill down to a reasonable level is by offering the chip blocks to slot into the ASIC, avoiding the reinvention of wheels. Marvell's already done all the hard work needed to produce tried-and-tested Ethernet PHY and controllers, NVMe storage managers, packet switches, memory interfaces, and so on. That alone "vaporizes" cost for the customer, O’Buckley told us.
Said customers are hoped to include 5G carriers, enterprise networking device makers, aerospace and defense giants, hyperscale and upper-tier cloud providers, and perhaps even automaker suppliers one day.
Finally, Marvell said this offering was made possible due in part to its acquisition of chip customization biz Avera last year, which was spun out of GlobalFoundries in 2018. GlobalFoundries had picked up Avera from IBM. ®