RISC-V processor specialist SiFive will double down on improving its CPU cores after pushing its system-on-chip design efforts into a new unit.
Dubbed OpenFive, the operation will design whatever system-on-chips customers need, supporting whichever CPU cores fit the individual applications. Crucially, that means OpenFive will design chips that can use RISC-V or rival Arm cores, or a mix of both, or something else entirely.
SiFive is the RISC-V world's problem solver: you can license its RISC-V CPU cores and system-on-chip building blocks; it can design whole RISC-V-based SoCs and ASICs for you; it can help you get them manufactured; and it shares a lot of its work as open source. It also sells RISC-V development boards featuring its silicon. It is all in on the RISC-V instruction set architecture (ISA), which is relatively young yet promising and open.
Now, SiFive's moved its system-on-chip and ASIC work into OpenFive. We understand that though OpenFive is described as "self-contained and autonomous," it is still a business unit of SiFive Inc. As a spokesperson put it: "SiFive will deepen its focus on RISC-V intellectual property, while OpenFive expands its opportunity for domain-specific silicon."
That means while SiFive works away on RISC-V cores that compete primarily against Arm, OpenFive will draw up for customers SoCs that may use said Arm cores – the "open" bit refers to its openness in terms of architecture choice. "OpenFive is open by being processor ISA agnostic, to enable the use of heterogeneous ISA designs to solve computing problems," Dr Naveed Sherwani, SiFive's CEO and president, told us.
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The skeptical among you may see this as SiFive waving the white flag and signalling a RISC-V-only design house is unsustainable in a semiconductor world dominated by Arm in the embedded corner at least, and that right now there is too much momentum in Arm's direction.
On the other hand, it's a sign that SiFive, a five-year-old startup, isn't blinkered: if its customers want chips with either Arm or RISC-V inside, or both or none, it will design those chips, take the money, and win them over to RISC-V later. This appears to be SiFive's thinking. Give clients a choice, let them mix and choose architectures, and eventually, maybe, they'll ditch Arm for RISC-V, if not already. Part of this argument is that RISC-V cores are customizable, and can be extended with extra sets of instructions, and this flexibility may lead to customers leaning away from Arm, which mostly forbids customization of its cores.
"This step accelerates the development of the software and application ecosystems to enable RISC-V-based designs become a majority ISA in any given application," Dr Sherwani told us when we questioned the goal of OpenFive.
"Through increased adoption and winning increasing numbers of functions inside a processor, RISC-V will be the choice for consolidation in the future. Migrating ISAs requires measured investment and support, but the open nature of RISC-V increases the auditability of proposed solutions, while the customizable nature of RISC-V makes targeted replacement of cores with domain-specific designs with advantages in power, performance, and area a better strategy."
"OpenFive customers can select any ISA processor core they need to meet their requirements," the CEO added, "along with the SoC IP and design expertise they require."
It's also worth pointing out that a couple of years ago, SiFive acquired a system-on-chip designer called Open-Silicon, which is an expert in crafting chips that use Arm cores. Thus, the formation of OpenFive allows that commercial work to continue in its own contained, ISA-agnostic unit while the SiFive parent takes care of the RISC-V side. In effect, the Arm-friendly services of Open-Silicon will continue under OpenFive, it appears.
SiFive claims at least some parts of its system-on-chip blueprints have gone into 150 million shipped components to date. OpenFive, led by Dr Shafy Eltoukh, will seemingly inherit this portfolio, which includes:
- A low-latency high-throughput Interlaken fabric interconnect for chip-to-chip or die-to-die connectivity
- HBM2/E high-bandwidth memory controller and PHY
- 400/800G Ethernet IP for data-center, networking, and supercomputer hardware
- USB subsystem spanning second-generation USB 3.1 to USB 2.0, including PHY, for consumer or edge devices
- Die-to-die controller IP for next-generation heterogeneous chiplet-style products
Last week, SiFive bagged a further $61m in funding, led by memory chip maker SK hynix and with cash from previous investors Western Digital, Qualcomm, and Intel. And last month, it announced an update to its blueprints, dubbed the 20G1 release, that it said improved performance, reduced die area, and lowered power consumption for certain cores. ®