Microsoft cooking Azure instance types just for chip designers

Ties up with TSMC on innovation lab and banks on elasticity speeding up design pipeline


Microsoft is cooking up specific Azure instance types optimised for Electronics Design Automation, as part of a new collaboration Taiwan Semiconductor Manufacturing Company (TSMC).

The two companies have pledged to together create a “Joint Innovation Lab to accelerate silicon design on Azure”.

As is ever the case with such Labs, the two companies are talking up how each is wonderful and that working together will create a gestalt capable of even greater wonders.

But Microsoft has said also said something a little more interesting, as follows:

We are working to optimize new VM types in all aspects of CPU performance, number of cores, memory-to-core ratio, and local storage, combined with the most effective storage options, targeting EDA workloads of highly complicated IC designs enabled by the most advanced process technologies.

Microsoft is also working on “cloud-optimized design solutions, tools, and methodologies combined, to fully utilize EDA parallelism.”

That’s interesting because while Microsoft and other big cloud operators do offer instance types suited to particular applications, they seldom do so for workloads quite so specific as EDA. Microsoft therefore clearly sees big opportunities in the field, or perhaps a field clear of competitors.

Microsoft sees its investment as helping silicon designers to get more work done, faster, by giving them more resources than they can run on-premises.

“It is not uncommon for EDA design jobs to take months due to in-house compute limitations,” wrote Rani Borkar, Microsoft’s corporate veep for Azure Hardware Systems and Infrastructure. “With access to Azure’s burstable resources to scale to tens of thousands of cores quickly, silicon designers are now able to achieve much faster time to market with improved efficiencies while dealing with their surge demand.”

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