DARPA picks Intel to automate conversion of FPGAs into ASICs for military applications

Chipzilla hints at bringing 10nm ASIC FAB to US soil to sate desire for faster and cheaper custom silicon

The United States’ Defense Advanced Research Projects Agency (DARPA) has announced an effort to “expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems.”

Intel was named as the only commercial partner of the effort, named Structured Array Hardware for Automatically Realized Applications program – aka project SAHARA. Boffins from University of Florida, University of Maryland, and Texas A&M are also aboard.

The project’s aim is simple: DARPA knows that field programmable gate arrays (FPGAs) are a fine way to create the kind of custom silicon needed for specialised defence applications, while also adding enough novelty to designs that enemies face a tougher target. But the research house also noted that “Structured application-specific integrated circuits (ASICs) deliver significantly higher performance and lower power consumption.”

So why not just take designs made on FPGAs and turn them into ASICs?

“Manually converting FPGAs to Structured ASICs … is a complex, lengthy, and costly process, making it difficult to justify the economic burden at the volume of custom chips required by DoD applications,” DARPA laments.

Enter Intel and the boffins, which have collectively been asked to “dramatically shorten the design process, reduce associated engineering costs, and enhance chip security” by figuring out how to “automate the conversion process for both currently fielded FPGAs as well as future capabilities, while adding unique chip protections to address supply chain security threats.”

Those protections include “security countermeasures capable of thwarting reverse engineering and counterfeiting attacks.”

“The research teams aim to develop novel chip protections and employ verification, validation, and red teaming to stress test the resulting measures,” DARPA says. “Once proven, it is anticipated that the countermeasures will be integrated into Intel’s Structured ASIC design flow.”

And more of that design flow will happen on US soil, because DARPA says “Intel aims to establish domestic manufacturing capabilities for the Structured ASICs on their 10nm process.”

Intel says its eASIC product is the tech for the job, on grounds that it is "an intermediary technology between FPGAs and standard-cell ASICs" and offers "faster time to market and lower non-recurring engineering cost compared with standard-cell ASICs."

Project SAHARA sounds like good news for the US military, but less welcome news for AMD which has just splashed $35bn on FPGA specialist Xilinx.

SAHARA is designed to support the US Department of Defense’s microelectronics Roadmap, and to work alongside the Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) effort and the State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects. ®