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Samsung aims first 512GB DDR5 DRAM chip built on High-K/Metal Gate tech at HPC, AI markets

Double the bandwidth of DDR4, with 13% less power consumption

Samsung has unveiled its first DDR5 DRAM based on a High-K/Metal Gate (HKMG) process, debuting with a 512GB module aimed at the high-performance computing and AI markets.

The DDR5 spec, which was finalised in mid-2020, allows for significantly higher capacity DIMMs and larger bandwidth than its predecessor. Samsung claimed its latest module provides peak transfer rates of 7,200 megabits per second, which we're told is more than double the bandwidth typically offered by the fastest DDR4 DRAM.

That's higher than JEDEC's initial DDR5 specification of 4,800Mbps, and more than double DDR4's 3,200Mbps.

Samsung wasn't the first vendor to cross the 512GB mark. Intel launched a 512GB DDR4 Optane module in 2019. Sammy is, however, the first to do so within the DDR5 field, and the first to use HKMG tech in the process, which Samsung claimed allowed it to achieve a 13 per cent power reduction against comparable modules.

Semiconductors of all stripes – from memory chips to computer processors – use something called a gate dielectric to insulate against electrical leakage. Previous gate dielectrics were based on a thin layer of silicon dioxide, which progressively shrunk in space with the miniaturisation of transistors. As this layer gets thinner, it becomes less effective, resulting in reliability and power consumption issues. This is undesirable considering that one of the major reasons to move to a smaller node is to reduce power draw.

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HKMG dielectrics are, put simply, more effective than silicon oxide ones, with hafnium-based materials frequently used. The "k" in High-K merely stands for Kappa, which is used as shorthand to refer to the dielectric constant.

Samsung first used HKMG tech in 2018 with its GDDR5 memory, although its origins span back further than that. While it got its start in the memory industry, with Micron doing much of the initial R&D legwork, Intel was among the first mass-adopters, jumping on the bandwagon as it switched to the 45nm process. Use of HKMG has now become widespread in the logic semiconductor industry, with IBM and TSMC notable adopters.

The 512GB module also uses TSV (through-silicon via) technology to achieve its high memory density. This approach sees chips stacked on top of each other to reduce amount of PCB real-estate consumed, while achieving faster overall performance due to the shorter distance electrons are required to travel between components.

In this case, Samsung has grouped eight 16GB DDR5 modules into a single 128GB logical unit, which can be arranged into a maximum 512GB configuration.

Commenting, Young-Soo Sohn, veep of Samsung's DRAM memory planning and enabling group, expressed hope the modules would find a home in medical research, financial services, autonomous driving, and smart cities.

"As the amount of data to be moved, stored and processed increases exponentially, the transition to DDR5 comes at a critical inflection point for cloud data centers, networks and edge deployments," added Carolyn Duran, memory and IO technology veep at Intel, in a statement.

Samsung has begun sampling its 512GB module for verification and certification. It did not say when customers can expect availability. ®

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